Commit Graph

226 Commits

Author SHA1 Message Date
tevador 2c87a058ec Support for multithreaded dataset initialization 2019-04-13 21:29:51 +02:00
tevador 9c383dc2ba Added superscalar-stats
Fixed makefile
2019-04-13 12:02:08 +02:00
tevador 53d272c6a9 Merge branch 'feature/light-code-gen' into dev 2019-04-12 19:36:44 +02:00
tevador 8c37d4aac3 More refactoring 2019-04-12 19:36:08 +02:00
tevador 9404516dd8 Refactoring 2019-04-12 14:56:20 +02:00
tevador d49302561f Refactoring + comments 2019-04-12 13:32:22 +02:00
tevador 24a22c6b54 Code generator refactoring 2019-04-12 00:02:22 +02:00
tevador 37ff37cd11 msvc solution 2019-04-11 20:46:35 +02:00
tevador 2e68c89740 Separate executeSuperscalar function
Tweaked superscalar hash constants
2019-04-11 18:31:13 +02:00
tevador 2132e5fef5 SuperscalarHash interpreter
Linux assembly code
2019-04-11 00:01:22 +02:00
tevador b4c02051fa Reworked SuperscalarHash instruction set
ASM and C code generator for SuperscalarHash
Support for Superscalar hash in the light mode
2019-04-07 15:38:51 +02:00
tevador 6e3136b37f Fixed cache alignment
Performance tuning
2019-04-06 17:07:40 +02:00
tevador 77dbe14658 SuperscalarHash JIT compiler
(unfinished)
2019-04-06 12:00:56 +02:00
tevador 690707ef49 Reworked addition instructions
Some bug fixes
2019-04-03 14:06:59 +02:00
tevador 2aaec84931 Bug fixes, trace output 2019-04-03 09:53:25 +02:00
tevador 428b845a3d Fixed an infinite loop bug 2019-04-01 19:04:08 +02:00
tevador 23a357db37 Removed optimizable instruction sequences 2019-04-01 18:31:02 +02:00
tevador 2b9209346e Operand allocation 2019-04-01 00:38:17 +02:00
tevador acef5ea0d7 Port mapping 2019-03-31 21:22:36 +02:00
tevador 2fd0a125b5 Front-end simulation 2019-03-31 13:32:16 +02:00
tevador 1c9ad90a96 Removed unused AES key expansion code 2019-03-29 08:57:47 +01:00
tevador ad7b473388 Updated readme 2019-03-28 16:40:53 +01:00
tevador 59bbb572c2 WIP 2019-03-28 15:27:10 +01:00
tevador 2bb42637fd Epoch increased to 2048 blocks 2019-03-22 14:03:13 +01:00
tevador 107270d93d Reduced Dataset size to 2 GiB with 8 memory accesses per block
Disabled Dataset growth
2019-03-22 12:53:16 +01:00
tevador 233af9f14f Minor fixes for non-x86 platforms 2019-03-22 12:03:39 +01:00
tevador 4c1ae951de Merge branch 'feature/branches' into dev
Conflicts:
	src/JitCompilerX86.cpp
	src/JitCompilerX86.hpp
	src/main.cpp
2019-03-22 11:53:48 +01:00
tevador 28ed776fbe Light JIT compiler - Linux 2019-03-22 11:00:21 +01:00
tevador 73a11f5c01 CompiledLightVirtualMachine 2019-03-21 20:44:59 +01:00
tevador 00368cae02 Fixed stats compilation 2019-03-21 09:17:28 +01:00
tevador 007f8599b9 Implemented branches in the interpreter
Fixed x86 immediate encoding
2019-03-20 23:38:37 +01:00
tevador 1617d8e34e Fixed squareHash reference 2019-03-20 00:36:12 +01:00
tevador 1945aae9f8 align -> balign 2019-03-19 22:27:17 +01:00
tevador 174754cb2b Added branches - ASM and JIT only 2019-03-17 23:09:11 +01:00
tevador 6b344b81fd initBlock asm version (disabled) 2019-03-17 00:57:48 +01:00
tevador 91063aac91 Reference result 2019-03-16 20:59:42 +01:00
tevador 344f365c42 Updated constants according to the specs 2019-03-16 00:10:09 +01:00
tevador edde7672e0 initBlock: cycle columns, asm implementation 2019-03-15 18:00:51 +01:00
tevador a1dc094c19 added epoch lag configuration 2019-03-11 23:43:52 +01:00
tevador 958d2bdc15 Fixed non-portable deserialization 2019-03-11 23:04:34 +01:00
tevador 2edf05cedc Implemented Dataset size increase per epoch 2019-03-10 23:14:03 +01:00
tevador e65d9da66c Configurable parameters separated into configuration.h 2019-03-08 15:34:34 +01:00
tevador 096a7c0d7b Implemented virtual memory free
Removed legacy AES code
2019-03-08 11:46:03 +01:00
tevador 6e8c83fdb6 Fixed softAes compilation on PowerPC 2019-02-25 13:17:26 +01:00
tevador 7c012b4fee Fixed non-portable nonce serialization
updated program.inc
2019-02-25 09:31:35 +01:00
tevador d9bc6cfeda Updated JIT compiler and assembly generator for new int -> float conversion 2019-02-24 17:24:06 +01:00
tevador 790b382eda Reworked conversion int -> float for register group E 2019-02-24 14:48:07 +01:00
tevador f3b114af88 Replaced division instructions with IMUL_RCP 2019-02-22 17:48:26 +01:00
tevador 9d5f621d5c Removed divideByConstantCodegen 2019-02-22 13:47:47 +01:00
tevador d9fcb34138 Fixed big endian load/store 2019-02-20 12:56:34 +01:00
tevador 88cf9d0728 Fixed 32-bit Windows build 2019-02-19 23:12:56 +01:00
tevador 219efce06c New command line options 2019-02-19 22:47:45 +01:00
tevador f930d5d4dc Fixed a bug in FSWAP_R 2019-02-18 22:09:20 +01:00
tevador c5309fae9e Fixed portable intrinsics compilation 2019-02-18 17:57:54 +01:00
tevador bf34d27ecd Portable SSE2 intrinsics 2019-02-18 08:56:37 +01:00
tevador 954365634e Fixed alignment of VirtualMachine 2019-02-18 08:54:55 +01:00
tevador dce8c74fa8 Fixed software AES in getResult 2019-02-18 08:45:39 +01:00
tevador 9a23bdb40d Fixed linux version of SquareHash 2019-02-18 08:44:28 +01:00
tevador bfd557dac5 Added reference result
Fixed undefined initial rounding mode
2019-02-17 10:54:51 +01:00
tevador 923420f0a3 Fixed mining and verification mode not giving the same results
Trace support in Assembly generator
2019-02-16 23:18:45 +01:00
tevador a145caa185 Fixed JIT compiler not producing the same code as genAsm and genNative 2019-02-15 16:43:52 +01:00
tevador f0d52fcf4d Fixed dependent constants 2019-02-15 11:38:20 +01:00
tevador ff0c5a58b3 More compact bytecode 2019-02-15 11:14:40 +01:00
tevador 447e8a1d4f Simplified division in interpreted mode
Fixed incorrect condition code in JitCompilerX86
Refactoring
2019-02-15 10:41:02 +01:00
tevador 1df975e583 Restored software AES support 2019-02-13 22:46:32 +01:00
tevador f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult 2019-02-13 00:01:34 +01:00
tevador 376c868ca0 Fixed wrong REX prefix in FDIV_M code 2019-02-12 23:20:10 +01:00
tevador 5a89c9b28e Use allocExecutableMemory 2019-02-12 18:18:02 +01:00
tevador 0b1761a846 Refactoring: mining/verification mode 2019-02-11 18:57:42 +01:00
tevador 69764966c0 Position independent loads fixed #21 2019-02-11 18:13:03 +01:00
tevador b8ce504be6 Added comments to hashAes1Rx4 and fillAes1Rx4
Fixed gcc compilation
Added performance numbers
2019-02-09 19:32:53 +01:00
tevador 2798d78717 Render imm32 as signed in RandomX code 2019-02-09 16:19:15 +01:00
tevador 32d827d0a6 Interpreter with bytecode
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
2019-02-09 15:45:26 +01:00
tevador a586751f6b Removed FPNEG instruction
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
2019-02-07 16:11:27 +01:00
tevador ac4462ad42 Renamed floating point instructions
Fixed negative source operand for FMUL_M and FDIV_M
2019-02-05 23:43:57 +01:00
tevador b417fd08ea 16 -> 8 chained programs
constant address loads are always from L3
2019-02-05 23:06:44 +01:00
tevador 1ee94bef2a Added ISWAP instruction
Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
2019-02-04 17:07:00 +01:00
tevador 20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador 8f2abd6c05 NOP instruction
register load/store from L3
2019-01-27 18:19:49 +01:00
tevador 005c67f64c Added explicit STORE instructions
JIT compiler
2019-01-27 10:52:30 +01:00
tevador d2cb086221 ASM code generator for "small" programs that fit into the uOP cache 2019-01-24 19:29:59 +01:00
tevador bd0dba88a8 4 scratchpad segments 2019-01-20 00:44:01 +01:00
tevador 16db607025 Scratchpad size increased to 1 MiB
New AES-based scratchpad hashing function
2019-01-18 23:51:18 +01:00
tevador 93c324709b Related to previous changes 2019-01-18 19:06:46 +01:00
tevador 89bc68d093 Memory-bound dataset initialization 2019-01-18 18:44:06 +01:00
tevador 4fb168e249 Large page support for cache
Bug fixes
2019-01-18 17:57:47 +01:00
tevador 8b1102ee05 Interpreter + async mode 2019-01-15 00:01:11 +01:00
tevador a7ffe8c19a Mix dataset cacheline with registers r0-r7 2019-01-13 21:14:59 +01:00
tevador 48d85643de Dataset intialization algorithm (AES) 2019-01-13 13:47:25 +01:00
tevador 67e741ff22 Reduced x86 code size by 512 bytes (and ecx -> and eax) 2019-01-12 20:27:35 +01:00
tevador 1426fcbab5 Print average program code size
Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
2019-01-12 16:05:09 +01:00
tevador 2756bcdcfe Added magic division to JIT compiler
New B operand selection rules
2019-01-11 16:53:52 +01:00
tevador 451dfc5730 Optimized division by constants 2019-01-11 14:08:21 +01:00
tevador c02ee4291d FPROUND - variable flag offset 2019-01-11 10:52:12 +01:00
tevador e487092f07 Simplified CALL and RET 2019-01-11 10:18:24 +01:00
tevador 557241cd95 JUMP instruction 2019-01-11 09:58:06 +01:00
tevador d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador b71e0eec65 Optimizations to reduce code size under 32K 2019-01-08 14:50:31 +01:00
tevador b6d654291f 90 address transformations 2019-01-08 12:19:19 +01:00
tevador 2f6a599ff6 Inlined calls for memory read 2019-01-07 17:44:43 +01:00
tevador 6519fed4d1 Combined prefetch + read into a single step 2019-01-07 11:26:43 +01:00
tevador 4189e4ebc6 Original number of VM instructions 2019-01-06 17:23:05 +01:00
tevador 619bee5418 Random dataset accesses - asm only
Initial support for large pages
2019-01-04 19:44:15 +01:00
tevador 3caecc7646 Vector FPU instructions
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
2018-12-31 19:06:45 +01:00
tevador a09bee8d60 js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up) 2018-12-28 14:18:41 +01:00
tevador 76b6b05cf2 Unconditional RET 2018-12-28 12:09:37 +01:00
tevador 39c569ae44 Fixed a potential crash in JitCompilerX86 2018-12-27 21:42:38 +01:00
tevador 5bc26348f1 Updated readme with performance data
Added --help option
2018-12-23 18:02:17 +01:00
tevador 03913d0e81 Run a single thread synchronously 2018-12-23 15:12:54 +01:00
tevador c05947db09 Bug fixes 2018-12-23 14:25:22 +01:00
tevador ca59925495 JitCompilerX86: use mmap to allocate an executable buffer
compile as c++11
2018-12-23 14:09:09 +01:00
tevador 740c40b218 8 branch conditions for CALL/RET 2018-12-21 22:41:35 +01:00
tevador 55afe9646f Debuggable assembly generator 2018-12-21 21:09:55 +01:00
tevador fce6e75689 Fixed copyright notice 2018-12-21 21:04:35 +01:00
tevador ffa67295c4 Instruction statistics 2018-12-20 22:42:47 +01:00
tevador 1db7dd6e8b Renamed immediate constants 2018-12-20 18:36:09 +01:00
tevador b9d2d853aa Support for multiple threads 2018-12-19 21:54:44 +01:00
tevador cb12feaf91 t1ha2 hash for scratchpad digest 2018-12-19 12:38:10 +01:00
tevador ed0bc906d6 JIT compiler for x86 2018-12-18 22:00:58 +01:00
tevador ddc29cb4d3 Optimized x86 initialization 2018-12-16 15:10:03 +01:00
tevador 4f276541d2 Modified x86 register allocation 2018-12-16 13:43:18 +01:00
tevador 6332831ec1 Implemented cache shift
Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
2018-12-15 23:13:17 +01:00
tevador d6ca408ce2 Merge branch 'master' of git@github.com:tevador/RandomX.git 2018-12-13 23:16:04 +01:00
tevador cb0721056a Assembly code generator for Windows 64-bit 2018-12-13 23:11:55 +01:00
Edward Vielmetti 8ef8224270
update ifdef for _rotr on aarch64
Enables compilation on aarch64 (Packet c1.large.arm)
2018-12-12 07:54:33 -05:00
tevador c9102ee88c RandomX portable interpreter 2018-12-11 21:00:30 +01:00