mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-08-15 00:23:14 +00:00
Bug fixes, trace output
This commit is contained in:
tevador
parent
428b845a3d
commit
2aaec84931
3 changed files with 115 additions and 73 deletions
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@ -62,6 +62,10 @@ namespace RandomX {
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constexpr int COND_R = IROR_R + RANDOMX_FREQ_IROR_R + RANDOMX_FREQ_IROL_R + RANDOMX_FREQ_ISWAP_R + RANDOMX_FREQ_FSWAP_R + RANDOMX_FREQ_FADD_R + RANDOMX_FREQ_FADD_M + RANDOMX_FREQ_FSUB_R + RANDOMX_FREQ_FSUB_M + RANDOMX_FREQ_FSCAL_R + RANDOMX_FREQ_FMUL_R + RANDOMX_FREQ_FDIV_M + RANDOMX_FREQ_FSQRT_R;
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}
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static bool isMul(uint8_t opcode) {
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return opcode == LightInstructionOpcode::IMUL_R || opcode == LightInstructionOpcode::IMULH_R || opcode == LightInstructionOpcode::ISMULH_R || opcode == LightInstructionOpcode::IMUL_RCP;
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}
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const int lightInstructionOpcode[] = {
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LightInstructionOpcode::IADD_R,
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LightInstructionOpcode::IADD_R,
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@ -344,7 +348,7 @@ namespace RandomX {
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const LightInstructionInfo LightInstructionInfo::IADD_C = LightInstructionInfo("IADD_C", LightInstructionType::IADD_C, MacroOp::Add_ri, -1);
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const LightInstructionInfo LightInstructionInfo::IADD_RC = LightInstructionInfo("IADD_RC", LightInstructionType::IADD_RC, MacroOp::Lea_sib, 0);
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const LightInstructionInfo LightInstructionInfo::ISUB_R = LightInstructionInfo("ISUB_R", LightInstructionType::ISUB_R, MacroOp::Sub_rr, 0);
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const LightInstructionInfo LightInstructionInfo::IMUL_9C = LightInstructionInfo("IMUL_9C", LightInstructionType::IMUL_9C, MacroOp::Lea_sib, 0);
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const LightInstructionInfo LightInstructionInfo::IMUL_9C = LightInstructionInfo("IMUL_9C", LightInstructionType::IMUL_9C, MacroOp::Lea_sib, -1);
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const LightInstructionInfo LightInstructionInfo::IMUL_R = LightInstructionInfo("IMUL_R", LightInstructionType::IMUL_R, MacroOp::Imul_rr, 0);
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const LightInstructionInfo LightInstructionInfo::IMUL_C = LightInstructionInfo("IMUL_C", LightInstructionType::IMUL_C, MacroOp::Imul_rri, -1);
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const LightInstructionInfo LightInstructionInfo::IMULH_R = LightInstructionInfo("IMULH_R", LightInstructionType::IMULH_R, IMULH_R_ops_array, 1, 0, 1);
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@ -434,7 +438,7 @@ namespace RandomX {
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const LightInstructionInfo* slot_3L[] = { &LightInstructionInfo::IADD_R, &LightInstructionInfo::ISUB_R, &LightInstructionInfo::IXOR_R, &LightInstructionInfo::IMULH_R, &LightInstructionInfo::ISMULH_R, &LightInstructionInfo::IXOR_R, &LightInstructionInfo::IMULH_R, &LightInstructionInfo::ISMULH_R };
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const LightInstructionInfo* slot_3F[] = { &LightInstructionInfo::IADD_R, &LightInstructionInfo::ISUB_R, &LightInstructionInfo::IXOR_R, &LightInstructionInfo::IROR_R };
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const LightInstructionInfo* slot_4[] = { &LightInstructionInfo::IMUL_R, &LightInstructionInfo::IROR_C };
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const LightInstructionInfo* slot_7[] = { &LightInstructionInfo::IADD_C, &LightInstructionInfo::IMUL_C, &LightInstructionInfo::IXOR_C, &LightInstructionInfo::IMUL_C };
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const LightInstructionInfo* slot_7[] = { &LightInstructionInfo::IADD_C, &LightInstructionInfo::IMUL_C, &LightInstructionInfo::IXOR_C, &LightInstructionInfo::IADD_C };
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const LightInstructionInfo* slot_7L = &LightInstructionInfo::COND_R;
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const LightInstructionInfo* slot_8[] = { &LightInstructionInfo::IADD_RC, &LightInstructionInfo::IMUL_9C };
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const LightInstructionInfo* slot_10 = &LightInstructionInfo::IMUL_RCP;
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@ -686,77 +690,95 @@ namespace RandomX {
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const LightInstruction LightInstruction::Null = LightInstruction(&LightInstructionInfo::NOP);
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constexpr int ALU_COUNT_MUL = 1;
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constexpr int ALU_COUNT = 4;
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constexpr int ALU_COUNT = 3;
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constexpr int LIGHT_OPCODE_BITS = 4;
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constexpr int V4_SRC_INDEX_BITS = 3;
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constexpr int V4_DST_INDEX_BITS = 3;
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constexpr int CYCLE_MAP_SIZE = RANDOMX_LPROG_LATENCY + 3;
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constexpr bool TRACE = true;
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static int blakeCounter = 0;
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static int scheduleUop(const MacroOp& mop, ExecutionPort::type(&portBusy)[RANDOMX_LPROG_LATENCY + 1][3], int cycle, int depCycle) {
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template<bool commit>
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static int scheduleUop(const MacroOp& mop, ExecutionPort::type(&portBusy)[CYCLE_MAP_SIZE][3], int cycle, int depCycle) {
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if (mop.isDependent()) {
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cycle = std::max(cycle, depCycle);
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}
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if (mop.isEliminated()) {
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std::cout << "; (eliminated)" << std::endl;
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if (commit)
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if (TRACE) std::cout << "; (eliminated)" << std::endl;
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return cycle;
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}
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else if (mop.isSimple()) {
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if (mop.getUop1() <= ExecutionPort::P5) {
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for (; cycle <= RANDOMX_LPROG_LATENCY; ++cycle) {
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for (; cycle < CYCLE_MAP_SIZE; ++cycle) {
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if (!portBusy[cycle][mop.getUop1() - 1]) {
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std::cout << "; P" << mop.getUop1() - 1 << " at cycle " << cycle << std::endl;
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portBusy[cycle][mop.getUop1() - 1] = mop.getUop1();
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if (commit) {
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if (TRACE) std::cout << "; P" << mop.getUop1() - 1 << " at cycle " << cycle << std::endl;
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portBusy[cycle][mop.getUop1() - 1] = mop.getUop1();
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}
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return cycle;
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}
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}
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}
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else if (mop.getUop1() == ExecutionPort::P05) {
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for (; cycle <= RANDOMX_LPROG_LATENCY; ++cycle) {
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for (; cycle < CYCLE_MAP_SIZE; ++cycle) {
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if (!portBusy[cycle][0]) {
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std::cout << "; P0 at cycle " << cycle << std::endl;
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portBusy[cycle][0] = mop.getUop1();
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if (commit) {
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if (TRACE) std::cout << "; P0 at cycle " << cycle << std::endl;
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portBusy[cycle][0] = mop.getUop1();
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}
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return cycle;
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}
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if (!portBusy[cycle][2]) {
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std::cout << "; P2 at cycle " << cycle << std::endl;
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portBusy[cycle][2] = mop.getUop1();
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if (commit) {
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if (TRACE) std::cout << "; P2 at cycle " << cycle << std::endl;
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portBusy[cycle][2] = mop.getUop1();
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}
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return cycle;
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}
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}
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}
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else {
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for (; cycle <= RANDOMX_LPROG_LATENCY; ++cycle) {
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for (; cycle < CYCLE_MAP_SIZE; ++cycle) {
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if (!portBusy[cycle][0]) {
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std::cout << "; P0 at cycle " << cycle << std::endl;
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portBusy[cycle][0] = mop.getUop1();
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if (commit) {
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if (TRACE) std::cout << "; P0 at cycle " << cycle << std::endl;
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portBusy[cycle][0] = mop.getUop1();
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}
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return cycle;
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}
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if (!portBusy[cycle][2]) {
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std::cout << "; P2 at cycle " << cycle << std::endl;
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portBusy[cycle][2] = mop.getUop1();
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if (commit) {
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if (TRACE) std::cout << "; P2 at cycle " << cycle << std::endl;
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portBusy[cycle][2] = mop.getUop1();
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}
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return cycle;
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}
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if (!portBusy[cycle][1]) {
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std::cout << "; P1 at cycle " << cycle << std::endl;
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portBusy[cycle][1] = mop.getUop1();
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if (commit) {
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if (TRACE) std::cout << "; P1 at cycle " << cycle << std::endl;
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portBusy[cycle][1] = mop.getUop1();
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}
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return cycle;
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}
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}
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}
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}
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else {
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for (; cycle <= RANDOMX_LPROG_LATENCY; ++cycle) {
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for (; cycle < CYCLE_MAP_SIZE; ++cycle) {
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if (!portBusy[cycle][mop.getUop1() - 1] && !portBusy[cycle][mop.getUop2() - 1]) {
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std::cout << "; P" << mop.getUop1() - 1 << " P" << mop.getUop2() - 1 << " at cycle " << cycle << std::endl;
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portBusy[cycle][mop.getUop1() - 1] = mop.getUop1();
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portBusy[cycle][mop.getUop2() - 1] = mop.getUop2();
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if (commit) {
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if (TRACE) std::cout << "; P" << mop.getUop1() - 1 << " P" << mop.getUop2() - 1 << " at cycle " << cycle << std::endl;
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portBusy[cycle][mop.getUop1() - 1] = mop.getUop1();
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portBusy[cycle][mop.getUop2() - 1] = mop.getUop2();
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}
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return cycle;
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}
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}
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}
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std::cout << "Unable to map operation '" << mop.getName() << "' to execution port";
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if (TRACE) std::cout << "Unable to map operation '" << mop.getName() << "' to execution port (cycle " << cycle << ")" << std::endl;
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return -1;
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}
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@ -773,7 +795,7 @@ namespace RandomX {
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void generateLightProg2(LightProgram& prog, const void* seed, int indexRegister, int nonce) {
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ExecutionPort::type portBusy[RANDOMX_LPROG_LATENCY + 1][3];
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ExecutionPort::type portBusy[CYCLE_MAP_SIZE][3];
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memset(portBusy, 0, sizeof(portBusy));
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RegisterInfo registers[8];
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Blake2Generator gen(seed, nonce);
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@ -784,9 +806,9 @@ namespace RandomX {
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int instrIndex = 0;
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int codeSize = 0;
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int macroOpCount = 0;
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int rxOpCount = 0;
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int cycle = 0;
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int depCycle = 0;
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int retireCycle = 0;
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int mopIndex = 0;
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bool portsSaturated = false;
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int outIndex = 0;
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@ -795,69 +817,72 @@ namespace RandomX {
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while(!portsSaturated) {
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fetchLine = fetchLine.fetchNext(currentInstruction.getType(), gen);
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std::cout << "; ------------- fetch cycle " << cycle << " (" << fetchLine.getName() << ")" << std::endl;
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if (TRACE) std::cout << "; ------------- fetch cycle " << cycle << " (" << fetchLine.getName() << ")" << std::endl;
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mopIndex = 0;
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while (!portsSaturated && mopIndex < fetchLine.getSize()) {
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while (mopIndex < fetchLine.getSize()) {
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int topCycle = cycle;
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if (instrIndex >= currentInstruction.getInfo().getSize()) {
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if (currentInstruction.getType() >= 0) {
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currentInstruction.toInstr(prog(outIndex++));
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}
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if (portsSaturated)
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break;
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currentInstruction = LightInstruction::createForSlot(gen, fetchLine.getCounts()[mopIndex], fetchLine.getSize() == mopIndex + 1, fetchLine.getIndex() == 0 && mopIndex == 0);
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instrIndex = 0;
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std::cout << "; " << currentInstruction.getInfo().getName() << std::endl;
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rxOpCount++;
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if (TRACE) std::cout << "; " << currentInstruction.getInfo().getName() << std::endl;
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}
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MacroOp& mop = currentInstruction.getInfo().getOp(instrIndex);
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if (fetchLine.getCounts()[mopIndex] != mop.getSize()) {
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std::cout << "ERROR instruction " << mop.getName() << " doesn't fit into slot of size " << fetchLine.getCounts()[mopIndex] << std::endl;
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if (TRACE) std::cout << "ERROR instruction " << mop.getName() << " doesn't fit into slot of size " << fetchLine.getCounts()[mopIndex] << std::endl;
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return;
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}
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std::cout << mop.getName() << " ";
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int scheduleCycle = scheduleUop(mop, portBusy, cycle, depCycle);
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if (TRACE) std::cout << mop.getName() << " ";
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int scheduleCycle = scheduleUop<false>(mop, portBusy, cycle, depCycle);
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mop.setCycle(scheduleCycle);
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if (scheduleCycle < 0) {
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if (TRACE) std::cout << "; Failed at cycle " << cycle << std::endl;
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return;
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}
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if (instrIndex == currentInstruction.getInfo().getSrcOp()) {
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for (attempts = 0; attempts < MAX_ATTEMPTS && !currentInstruction.selectSource(scheduleCycle, registers, gen); ++attempts) {
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std::cout << "; src STALL at cycle " << cycle << std::endl;
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if (TRACE) std::cout << "; src STALL at cycle " << cycle << std::endl;
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++scheduleCycle;
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++cycle;
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}
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if (attempts == MAX_ATTEMPTS) { //throw instruction away
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cycle = topCycle;
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//cycle = topCycle;
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instrIndex = currentInstruction.getInfo().getSize();
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std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl;
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if (TRACE) std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl;
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continue;
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}
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std::cout << "; src = r" << currentInstruction.getSource() << std::endl;
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if (TRACE) std::cout << "; src = r" << currentInstruction.getSource() << std::endl;
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}
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if (instrIndex == currentInstruction.getInfo().getDstOp()) {
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for (attempts = 0; attempts < MAX_ATTEMPTS && !currentInstruction.selectDestination(scheduleCycle, registers, gen); ++attempts) {
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std::cout << "; dst STALL at cycle " << cycle << std::endl;
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if (TRACE) std::cout << "; dst STALL at cycle " << cycle << std::endl;
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++scheduleCycle;
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++cycle;
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}
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if (attempts == MAX_ATTEMPTS) { //throw instruction away
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cycle = topCycle;
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//cycle = topCycle;
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instrIndex = currentInstruction.getInfo().getSize();
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std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl;
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if (TRACE) std::cout << "; THROW away " << currentInstruction.getInfo().getName() << std::endl;
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continue;
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}
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std::cout << "; dst = r" << currentInstruction.getDestination() << std::endl;
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if (TRACE) std::cout << "; dst = r" << currentInstruction.getDestination() << std::endl;
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}
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depCycle = scheduleCycle + mop.getLatency();
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if (instrIndex == currentInstruction.getInfo().getResultOp()) {
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int dst = currentInstruction.getDestination();
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RegisterInfo& ri = registers[dst];
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ri.latency = depCycle;
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retireCycle = depCycle;
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ri.latency = retireCycle;
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ri.lastOpGroup = currentInstruction.getGroup();
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ri.lastOpPar = currentInstruction.getGroupPar();
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std::cout << "; RETIRED at cycle " << depCycle << std::endl;
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if (TRACE) std::cout << "; RETIRED at cycle " << retireCycle << std::endl;
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}
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scheduleUop<true>(mop, portBusy, scheduleCycle, scheduleCycle);
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codeSize += mop.getSize();
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mopIndex++;
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instrIndex++;
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@ -866,43 +891,60 @@ namespace RandomX {
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portsSaturated = true;
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}
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cycle = topCycle;
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if (instrIndex >= currentInstruction.getInfo().getSize()) {
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currentInstruction.toInstr(prog(outIndex++));
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}
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}
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++cycle;
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}
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while (instrIndex < currentInstruction.getInfo().getSize()) {
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if (mopIndex >= fetchLine.getSize()) {
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fetchLine = fetchLine.fetchNext(currentInstruction.getType(), gen);
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std::cout << "; cycle " << cycle++ << " buffer " << fetchLine.getName() << std::endl;
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mopIndex = 0;
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}
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MacroOp& mop = currentInstruction.getInfo().getOp(instrIndex);
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std::cout << mop.getName() << " ";
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codeSize += mop.getSize();
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mopIndex++;
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instrIndex++;
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macroOpCount++;
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int scheduleCycle = scheduleUop(mop, portBusy, cycle, depCycle);
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mop.setCycle(scheduleCycle);
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depCycle = scheduleCycle + mop.getLatency();
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}
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std::cout << "; ALU port utilization:" << std::endl;
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std::cout << "; (*= in use, _ = idle)" << std::endl;
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std::cout << "; code size " << codeSize << std::endl;
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std::cout << "; x86 macro-ops: " << macroOpCount << std::endl;
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std::cout << "; RandomX instructions: " << rxOpCount << std::endl;
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for (int i = 0; i < RANDOMX_LPROG_LATENCY + 1; ++i) {
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std::cout << std::setw(3) << i << " ";
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int portCycles = 0;
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for (int i = 0; i < CYCLE_MAP_SIZE; ++i) {
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std::cout << "; " << std::setw(3) << i << " ";
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for (int j = 0; j < 3; ++j) {
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std::cout << (portBusy[i][j] ? '*' : '_');
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portCycles += !!portBusy[i][j];
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}
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std::cout << std::endl;
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}
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std::cout << "; code size " << codeSize << " bytes" << std::endl;
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std::cout << "; x86 macro-ops: " << macroOpCount << std::endl;
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std::cout << "; RandomX instructions: " << outIndex << std::endl;
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std::cout << "; Execution time: " << retireCycle << " cycles" << std::endl;
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std::cout << "; IPC = " << (macroOpCount / (double)retireCycle) << std::endl;
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std::cout << "; Port-cycles: " << portCycles << std::endl;
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int asicLatency[8];
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memset(asicLatency, 0, sizeof(asicLatency));
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int mulCount = 0;
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for (int i = 0; i < outIndex; ++i) {
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Instruction& instr = prog(i);
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int latDst = asicLatency[instr.dst] + 1;
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int latSrc = instr.dst != instr.src ? asicLatency[instr.src] + 1 : 0;
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asicLatency[instr.dst] = std::max(latDst, latSrc);
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mulCount += isMul(instr.opcode);
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}
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std::cout << "; Multiplications: " << mulCount << std::endl;
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std::cout << "; ASIC latency:" << std::endl;
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for (int i = 0; i < 8; ++i) {
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std::cout << "; r" << i << " = " << asicLatency[i] << std::endl;
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}
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std::cout << "; CPU latency:" << std::endl;
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for (int i = 0; i < 8; ++i) {
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std::cout << "; r" << i << " = " << registers[i].latency << std::endl;
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}
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prog.setSize(outIndex);
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}
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void generateLightProgram(LightProgram& prog, const void* seed, int indexRegister) {
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void generateLightProgram(LightProgram& prog, const void* seed, int indexRegister, int nonce) {
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// Source: https://www.agner.org/optimize/instruction_tables.pdf
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const int op_latency[LightInstructionType::COUNT] = { 1, 2, 1, 2, 3, 5, 5, 4, 1, 2, 5 };
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|
@ -20,6 +20,6 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
|
|||
#include "Program.hpp"
|
||||
|
||||
namespace RandomX {
|
||||
void generateLightProgram(LightProgram& prog, const void* seed, int indexRegister);
|
||||
void generateLightProgram(LightProgram& prog, const void* seed, int indexRegister, int nonce);
|
||||
void generateLightProg2(LightProgram& prog, const void* seed, int indexRegister, int nonce);
|
||||
}
|
||||
|
|
@ -226,7 +226,7 @@ int main(int argc, char** argv) {
|
|||
RandomX::generateLightProg2(p, seed, 0, programCount);
|
||||
RandomX::AssemblyGeneratorX86 asmX86;
|
||||
asmX86.generateProgram(p);
|
||||
std::cout << "-------------------------------------------------------" << std::endl;
|
||||
//std::ofstream file("lightProg2.asm");
|
||||
asmX86.printCode(std::cout);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue