Fixed mining and verification mode not giving the same results
Trace support in Assembly generator
This commit is contained in:
tevador
parent
a145caa185
commit
923420f0a3
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@ -58,6 +58,24 @@ namespace RandomX {
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}
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}
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void AssemblyGeneratorX86::traceint(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush " << regR[instr.dst] << std::endl;
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}
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}
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void AssemblyGeneratorX86::traceflt(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush 0" << std::endl;
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}
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}
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void AssemblyGeneratorX86::tracenop(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush 0" << std::endl;
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}
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}
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void AssemblyGeneratorX86::generateCode(Instruction& instr, int i) {
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asmCode << "\t; " << instr;
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auto generator = engine[instr.opcode];
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@ -86,6 +104,7 @@ namespace RandomX {
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else {
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asmCode << "\tadd " << regR[instr.dst] << ", " << (int32_t)instr.imm32 << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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@ -97,11 +116,13 @@ namespace RandomX {
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else {
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asmCode << "\tadd " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IADD_RC(Instruction& instr, int i) {
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.src] << std::showpos << (int32_t)instr.imm32 << std::noshowpos << "]" << std::endl;
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traceint(instr);
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}
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//1 uOP
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@ -112,6 +133,7 @@ namespace RandomX {
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", " << (int32_t)instr.imm32 << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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@ -123,11 +145,13 @@ namespace RandomX {
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else {
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asmCode << "\tsub " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_IMUL_9C(Instruction& instr, int i) {
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asmCode << "\tlea " << regR[instr.dst] << ", [" << regR[instr.dst] << "+" << regR[instr.dst] << "*8" << std::showpos << (int32_t)instr.imm32 << std::noshowpos << "]" << std::endl;
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traceint(instr);
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}
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//1 uOP
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@ -138,6 +162,7 @@ namespace RandomX {
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else {
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asmCode << "\timul " << regR[instr.dst] << ", " << (int32_t)instr.imm32 << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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@ -149,6 +174,7 @@ namespace RandomX {
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else {
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asmCode << "\timul " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//4 uOPs
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@ -156,6 +182,7 @@ namespace RandomX {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\tmul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//5.75 uOPs
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@ -170,6 +197,7 @@ namespace RandomX {
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asmCode << "\tmul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//4 uOPs
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@ -177,6 +205,7 @@ namespace RandomX {
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asmCode << "\tmov rax, " << regR[instr.dst] << std::endl;
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asmCode << "\timul " << regR[instr.src] << std::endl;
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//5.75 uOPs
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@ -191,11 +220,13 @@ namespace RandomX {
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asmCode << "\timul qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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asmCode << "\tmov " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_INEG_R(Instruction& instr, int i) {
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asmCode << "\tneg " << regR[instr.dst] << std::endl;
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traceint(instr);
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}
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//1 uOP
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@ -206,6 +237,7 @@ namespace RandomX {
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else {
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asmCode << "\txor " << regR[instr.dst] << ", " << (int32_t)instr.imm32 << std::endl;
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}
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traceint(instr);
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}
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//2.75 uOP
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@ -217,6 +249,7 @@ namespace RandomX {
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else {
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asmCode << "\txor " << regR[instr.dst] << ", qword ptr [rsi+" << genAddressImm(instr) << "]" << std::endl;
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}
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traceint(instr);
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}
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//1.75 uOPs
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@ -228,6 +261,7 @@ namespace RandomX {
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else {
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asmCode << "\tror " << regR[instr.dst] << ", " << (instr.imm32 & 63) << std::endl;
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}
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traceint(instr);
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}
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//1.75 uOPs
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@ -239,6 +273,7 @@ namespace RandomX {
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else {
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asmCode << "\trol " << regR[instr.dst] << ", " << (instr.imm32 & 63) << std::endl;
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}
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traceint(instr);
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}
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//~6 uOPs
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@ -273,7 +308,11 @@ namespace RandomX {
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if(shift > 0)
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asmCode << "\tshr " << regR[instr.dst] << ", " << shift << std::endl;
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}
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}
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traceint(instr);
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}
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else {
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tracenop(instr);
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}
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}
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//~8.5 uOPs
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@ -300,6 +339,7 @@ namespace RandomX {
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if (negative)
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asmCode << "\tneg rax" << std::endl;
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asmCode << "\tadd " << regR[instr.dst] << ", rax" << std::endl;
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traceint(instr);
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}
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else if (divisor != 0) {
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magics_info mi = compute_signed_magic_info(divisor);
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@ -325,6 +365,10 @@ namespace RandomX {
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asmCode << "\tsets al" << std::endl;
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asmCode << "\tadd rdx, rax" << std::endl;
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asmCode << "\tadd " << regR[instr.dst] << ", rdx" << std::endl;
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traceint(instr);
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}
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else {
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tracenop(instr);
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}
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}
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@ -332,12 +376,17 @@ namespace RandomX {
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void AssemblyGeneratorX86::h_ISWAP_R(Instruction& instr, int i) {
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if (instr.src != instr.dst) {
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asmCode << "\txchg " << regR[instr.dst] << ", " << regR[instr.src] << std::endl;
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traceint(instr);
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}
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else {
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tracenop(instr);
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}
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}
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//1 uOPs
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void AssemblyGeneratorX86::h_FSWAP_R(Instruction& instr, int i) {
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asmCode << "\tshufpd " << regFE[instr.dst] << ", " << regFE[instr.dst] << ", 1" << std::endl;
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traceflt(instr);
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}
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//1 uOP
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@ -346,6 +395,7 @@ namespace RandomX {
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instr.src %= 4;
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asmCode << "\taddpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
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//asmCode << "\t" << fsumInstr[instr.mod % 4] << " " << signMask << ", " << regF[instr.dst] << std::endl;
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traceflt(instr);
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}
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//5 uOPs
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@ -354,6 +404,7 @@ namespace RandomX {
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genAddressReg(instr);
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asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
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asmCode << "\taddpd " << regF[instr.dst] << ", xmm12" << std::endl;
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traceflt(instr);
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}
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//1 uOP
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@ -362,6 +413,7 @@ namespace RandomX {
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instr.src %= 4;
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asmCode << "\tsubpd " << regF[instr.dst] << ", " << regA[instr.src] << std::endl;
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//asmCode << "\t" << fsumInstr[instr.mod % 4] << " " << signMask << ", " << regF[instr.dst] << std::endl;
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traceflt(instr);
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}
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//5 uOPs
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@ -370,12 +422,14 @@ namespace RandomX {
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genAddressReg(instr);
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asmCode << "\tcvtdq2pd xmm12, qword ptr [rsi+rax]" << std::endl;
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asmCode << "\tsubpd " << regF[instr.dst] << ", xmm12" << std::endl;
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traceflt(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_FSCAL_R(Instruction& instr, int i) {
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instr.dst %= 4;
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asmCode << "\txorps " << regF[instr.dst] << ", " << signMask << std::endl;
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traceflt(instr);
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}
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//1 uOPs
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@ -383,6 +437,7 @@ namespace RandomX {
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instr.dst %= 4;
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instr.src %= 4;
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asmCode << "\tmulpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
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traceflt(instr);
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}
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//7 uOPs
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@ -393,6 +448,7 @@ namespace RandomX {
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asmCode << "\tandps xmm12, xmm14" << std::endl;
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asmCode << "\tmulpd " << regE[instr.dst] << ", xmm12" << std::endl;
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asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
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traceflt(instr);
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}
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//2 uOPs
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@ -401,6 +457,7 @@ namespace RandomX {
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instr.src %= 4;
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asmCode << "\tdivpd " << regE[instr.dst] << ", " << regA[instr.src] << std::endl;
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asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
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traceflt(instr);
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}
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//7 uOPs
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@ -411,12 +468,14 @@ namespace RandomX {
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asmCode << "\tandps xmm12, xmm14" << std::endl;
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asmCode << "\tdivpd " << regE[instr.dst] << ", xmm12" << std::endl;
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asmCode << "\tmaxpd " << regE[instr.dst] << ", " << dblMin << std::endl;
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traceflt(instr);
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}
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//1 uOP
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void AssemblyGeneratorX86::h_FSQRT_R(Instruction& instr, int i) {
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instr.dst %= 4;
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asmCode << "\tsqrtpd " << regE[instr.dst] << ", " << regE[instr.dst] << std::endl;
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traceflt(instr);
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}
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//6 uOPs
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@ -429,6 +488,7 @@ namespace RandomX {
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asmCode << "\tor eax, 40896" << std::endl;
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asmCode << "\tmov dword ptr [rsp-8], eax" << std::endl;
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asmCode << "\tldmxcsr dword ptr [rsp-8]" << std::endl;
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tracenop(instr);
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}
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static inline const char* condition(Instruction& instr) {
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@ -461,6 +521,7 @@ namespace RandomX {
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asmCode << "\tcmp " << regR32[instr.src] << ", " << (int32_t)instr.imm32 << std::endl;
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asmCode << "\tset" << condition(instr) << " cl" << std::endl;
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asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
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traceint(instr);
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}
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//6 uOPs
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@ -470,22 +531,26 @@ namespace RandomX {
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asmCode << "\tcmp dword ptr [rsi+rax], " << (int32_t)instr.imm32 << std::endl;
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asmCode << "\tset" << condition(instr) << " cl" << std::endl;
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asmCode << "\tadd " << regR[instr.dst] << ", rcx" << std::endl;
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traceint(instr);
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}
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//3 uOPs
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void AssemblyGeneratorX86::h_ISTORE(Instruction& instr, int i) {
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genAddressRegDst(instr);
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asmCode << "\tmov qword ptr [rsi+rax], " << regR[instr.src] << std::endl;
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tracenop(instr);
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}
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//3 uOPs
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void AssemblyGeneratorX86::h_FSTORE(Instruction& instr, int i) {
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genAddressRegDst(instr, 16);
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asmCode << "\tmovapd xmmword ptr [rsi+rax], " << regFE[instr.src] << std::endl;
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tracenop(instr);
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}
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void AssemblyGeneratorX86::h_NOP(Instruction& instr, int i) {
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asmCode << "\tnop" << std::endl;
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tracenop(instr);
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}
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#include "instructionWeights.hpp"
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@ -45,6 +45,10 @@ namespace RandomX {
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void generateCode(Instruction&, int);
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void traceint(Instruction&);
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void traceflt(Instruction&);
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void tracenop(Instruction&);
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void h_IADD_R(Instruction&, int);
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void h_IADD_M(Instruction&, int);
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void h_IADD_RC(Instruction&, int);
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@ -82,6 +82,31 @@ namespace RandomX {
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void InterpretedVirtualMachine::executeBytecode<ProgramLength>(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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}
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static void print(int_reg_t r) {
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std::cout << std::hex << std::setw(16) << std::setfill('0') << r << std::endl;
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}
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static void print(__m128d f) {
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uint64_t lo = *(((uint64_t*)&f) + 0);
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uint64_t hi = *(((uint64_t*)&f) + 1);
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std::cout << std::hex << std::setw(16) << std::setfill('0') << hi << '-' << std::hex << std::setw(16) << std::setfill('0') << lo << std::endl;
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}
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static void printState(int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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for (int i = 0; i < 8; ++i) {
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std::cout << "r" << i << " = "; print(r[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "f" << i << " = "; print(f[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "e" << i << " = "; print(e[i]);
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}
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for (int i = 0; i < 4; ++i) {
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std::cout << "a" << i << " = "; print(a[i]);
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}
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}
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FORCE_INLINE void InterpretedVirtualMachine::executeBytecode(int i, int_reg_t(&r)[8], __m128d (&f)[4], __m128d (&e)[4], __m128d (&a)[4]) {
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auto& ibc = byteCode[i];
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switch (ibc.type)
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@ -107,7 +132,7 @@ namespace RandomX {
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} break;
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case InstructionType::IMUL_9C: {
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*ibc.idst += 9 * *ibc.idst + ibc.imm;
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*ibc.idst += 8 * *ibc.idst + ibc.imm;
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} break;
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case InstructionType::IMUL_R: {
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@ -210,7 +235,7 @@ namespace RandomX {
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} break;
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case InstructionType::FDIV_M: {
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__m128d fsrc = load_cvt_i32x2(scratchpad + (*ibc.isrc & ibc.memMask));
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__m128d fsrc = _mm_abs(load_cvt_i32x2(scratchpad + (*ibc.isrc & ibc.memMask)));
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__m128d fdst = _mm_div_pd(*ibc.fdst, fsrc);
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*ibc.fdst = _mm_max_pd(fdst, _mm_set_pd(DBL_MIN, DBL_MIN));
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} break;
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@ -220,11 +245,11 @@ namespace RandomX {
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} break;
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case InstructionType::COND_R: {
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*ibc.idst += condition(*ibc.isrc, ibc.imm, ibc.condition) ? 1 : 0;
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*ibc.idst += condition(ibc.condition, *ibc.isrc, ibc.imm) ? 1 : 0;
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} break;
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case InstructionType::COND_M: {
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*ibc.idst += condition(load64(scratchpad + (*ibc.isrc & ibc.memMask)), ibc.imm, ibc.condition) ? 1 : 0;
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*ibc.idst += condition(ibc.condition, load64(scratchpad + (*ibc.isrc & ibc.memMask)), ibc.imm) ? 1 : 0;
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} break;
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case InstructionType::CFROUND: {
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@ -242,6 +267,13 @@ namespace RandomX {
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default:
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UNREACHABLE;
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}
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if (trace) {
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//std::cout << program(i);
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if(ibc.type < 20 || ibc.type == 31 || ibc.type == 32)
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print(*ibc.idst);
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else //if(ibc.type >= 20 && ibc.type <= 30)
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print(0);
|
||||
}
|
||||
}
|
||||
|
||||
void InterpretedVirtualMachine::execute() {
|
||||
|
|
@ -260,10 +292,20 @@ namespace RandomX {
|
|||
uint32_t spAddr0 = mem.mx;
|
||||
uint32_t spAddr1 = mem.ma;
|
||||
|
||||
if (trace) {
|
||||
std::cout << "execute (reg: r" << readReg0 << ", r" << readReg1 << ", r" << readReg2 << ", r" << readReg3 << ")" << std::endl;
|
||||
std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
|
||||
std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
|
||||
printState(r, f, e, a);
|
||||
}
|
||||
|
||||
for(unsigned iter = 0; iter < InstructionCount; ++iter) {
|
||||
//std::cout << "Iteration " << iter << std::endl;
|
||||
spAddr0 ^= r[readReg0];
|
||||
uint64_t spMix = r[readReg0] ^ r[readReg1];
|
||||
spAddr0 ^= spMix;
|
||||
spAddr0 &= ScratchpadL3Mask64;
|
||||
spAddr1 ^= spMix >> 32;
|
||||
spAddr1 &= ScratchpadL3Mask64;
|
||||
|
||||
r[0] ^= load64(scratchpad + spAddr0 + 0);
|
||||
r[1] ^= load64(scratchpad + spAddr0 + 8);
|
||||
|
|
@ -274,9 +316,6 @@ namespace RandomX {
|
|||
r[6] ^= load64(scratchpad + spAddr0 + 48);
|
||||
r[7] ^= load64(scratchpad + spAddr0 + 56);
|
||||
|
||||
spAddr1 ^= r[readReg1];
|
||||
spAddr1 &= ScratchpadL3Mask64;
|
||||
|
||||
f[0] = load_cvt_i32x2(scratchpad + spAddr1 + 0);
|
||||
f[1] = load_cvt_i32x2(scratchpad + spAddr1 + 8);
|
||||
f[2] = load_cvt_i32x2(scratchpad + spAddr1 + 16);
|
||||
|
|
@ -286,6 +325,14 @@ namespace RandomX {
|
|||
e[2] = _mm_abs(load_cvt_i32x2(scratchpad + spAddr1 + 48));
|
||||
e[3] = _mm_abs(load_cvt_i32x2(scratchpad + spAddr1 + 56));
|
||||
|
||||
if (trace) {
|
||||
std::cout << "iteration " << std::dec << iter << std::endl;
|
||||
std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
|
||||
std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
|
||||
printState(r, f, e, a);
|
||||
std::cout << "-----------------------------------" << std::endl;
|
||||
}
|
||||
|
||||
executeBytecode<0>(r, f, e, a);
|
||||
|
||||
if (asyncWorker) {
|
||||
|
|
@ -309,6 +356,14 @@ namespace RandomX {
|
|||
std::swap(mem.mx, mem.ma);
|
||||
}
|
||||
|
||||
if (trace) {
|
||||
std::cout << "iteration " << std::dec << iter << std::endl;
|
||||
std::cout << "spAddr " << std::hex << std::setw(8) << std::setfill('0') << spAddr1 << " / " << std::setw(8) << std::setfill('0') << spAddr0 << std::endl;
|
||||
std::cout << "ma/mx " << std::hex << std::setw(8) << std::setfill('0') << mem.ma << std::setw(8) << std::setfill('0') << mem.mx << std::endl;
|
||||
printState(r, f, e, a);
|
||||
std::cout << "===================================" << std::endl;
|
||||
}
|
||||
|
||||
store64(scratchpad + spAddr1 + 0, r[0]);
|
||||
store64(scratchpad + spAddr1 + 8, r[1]);
|
||||
store64(scratchpad + spAddr1 + 16, r[2]);
|
||||
|
|
@ -318,10 +373,15 @@ namespace RandomX {
|
|||
store64(scratchpad + spAddr1 + 48, r[6]);
|
||||
store64(scratchpad + spAddr1 + 56, r[7]);
|
||||
|
||||
_mm_store_pd((double*)(scratchpad + spAddr0 + 0), _mm_mul_pd(f[0], e[0]));
|
||||
_mm_store_pd((double*)(scratchpad + spAddr0 + 16), _mm_mul_pd(f[1], e[1]));
|
||||
_mm_store_pd((double*)(scratchpad + spAddr0 + 32), _mm_mul_pd(f[2], e[2]));
|
||||
_mm_store_pd((double*)(scratchpad + spAddr0 + 48), _mm_mul_pd(f[3], e[3]));
|
||||
f[0] = _mm_mul_pd(f[0], e[0]);
|
||||
f[1] = _mm_mul_pd(f[1], e[1]);
|
||||
f[2] = _mm_mul_pd(f[2], e[2]);
|
||||
f[3] = _mm_mul_pd(f[3], e[3]);
|
||||
|
||||
_mm_store_pd((double*)(scratchpad + spAddr0 + 0), f[0]);
|
||||
_mm_store_pd((double*)(scratchpad + spAddr0 + 16), f[1]);
|
||||
_mm_store_pd((double*)(scratchpad + spAddr0 + 32), f[2]);
|
||||
_mm_store_pd((double*)(scratchpad + spAddr0 + 48), f[3]);
|
||||
|
||||
spAddr0 = 0;
|
||||
spAddr1 = 0;
|
||||
|
|
@ -719,6 +779,7 @@ namespace RandomX {
|
|||
ibc.type = InstructionType::ISTORE;
|
||||
ibc.idst = &r[dst];
|
||||
ibc.isrc = &r[src];
|
||||
ibc.memMask = ((instr.mod % 4) ? ScratchpadL1Mask : ScratchpadL2Mask);
|
||||
} break;
|
||||
|
||||
CASE_REP(FSTORE) {
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ program_begin:
|
|||
|
||||
;# 256 instructions
|
||||
include program.inc
|
||||
|
||||
IF 1
|
||||
mov eax, r12d ;# read address register 1
|
||||
xor eax, r15d ;# read address register 2
|
||||
xor rbp, rax ;# modify "mx"
|
||||
|
|
@ -189,6 +189,26 @@ program_begin:
|
|||
movapd xmmword ptr [rcx+16], xmm1
|
||||
movapd xmmword ptr [rcx+32], xmm2
|
||||
movapd xmmword ptr [rcx+48], xmm3
|
||||
else
|
||||
; memcpy trace from stack to scratchpad
|
||||
mov rax, rsi
|
||||
mov rdx, rdi
|
||||
|
||||
cld
|
||||
mov rsi, rsp
|
||||
mov rdi, rax
|
||||
mov rcx, 1024
|
||||
|
||||
rep movsq
|
||||
|
||||
add rsp, 8192
|
||||
|
||||
pop rcx
|
||||
pop rcx
|
||||
|
||||
mov rsi, rax
|
||||
mov rdi, rdx
|
||||
endif
|
||||
sub ebx, 1
|
||||
jnz program_begin
|
||||
|
||||
|
|
|
|||
|
|
@ -183,6 +183,12 @@ void mine(RandomX::VirtualMachine* vm, std::atomic<int>& atomicNonce, AtomicHash
|
|||
fillAes1Rx4<softAes>((void*)hash, sizeof(RandomX::Program), vm->getProgramBuffer());
|
||||
vm->initialize();
|
||||
vm->execute();
|
||||
/*if (RandomX::trace) {
|
||||
for (int j = 0; j < RandomX::ProgramLength; ++j) {
|
||||
uint64_t res = *(uint64_t*)(scratchpad + 8 * (RandomX::ProgramLength - 1 - j));
|
||||
std::cout << std::hex << std::setw(16) << std::setfill('0') << res << std::endl;
|
||||
}
|
||||
}*/
|
||||
vm->getResult<softAes>(scratchpad, RandomX::ScratchpadSize, hash);
|
||||
result.xorWith(hash);
|
||||
if (RandomX::trace) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue