tevador
|
6519fed4d1
|
Combined prefetch + read into a single step
|
2019-01-07 11:26:43 +01:00 |
|
tevador
|
4189e4ebc6
|
Original number of VM instructions
|
2019-01-06 17:23:05 +01:00 |
|
tevador
|
619bee5418
|
Random dataset accesses - asm only
Initial support for large pages
|
2019-01-04 19:44:15 +01:00 |
|
tevador
|
3caecc7646
|
Vector FPU instructions
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
|
2018-12-31 19:06:45 +01:00 |
|
tevador
|
a09bee8d60
|
js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up)
|
2018-12-28 14:18:41 +01:00 |
|
tevador
|
76b6b05cf2
|
Unconditional RET
|
2018-12-28 12:09:37 +01:00 |
|
tevador
|
39c569ae44
|
Fixed a potential crash in JitCompilerX86
|
2018-12-27 21:42:38 +01:00 |
|
tevador
|
5bc26348f1
|
Updated readme with performance data
Added --help option
|
2018-12-23 18:02:17 +01:00 |
|
tevador
|
03913d0e81
|
Run a single thread synchronously
|
2018-12-23 15:12:54 +01:00 |
|
tevador
|
c05947db09
|
Bug fixes
|
2018-12-23 14:25:22 +01:00 |
|
tevador
|
ca59925495
|
JitCompilerX86: use mmap to allocate an executable buffer
compile as c++11
|
2018-12-23 14:09:09 +01:00 |
|
tevador
|
740c40b218
|
8 branch conditions for CALL/RET
|
2018-12-21 22:41:35 +01:00 |
|
tevador
|
55afe9646f
|
Debuggable assembly generator
|
2018-12-21 21:09:55 +01:00 |
|
tevador
|
fce6e75689
|
Fixed copyright notice
|
2018-12-21 21:04:35 +01:00 |
|
tevador
|
ffa67295c4
|
Instruction statistics
|
2018-12-20 22:42:47 +01:00 |
|
tevador
|
1db7dd6e8b
|
Renamed immediate constants
|
2018-12-20 18:36:09 +01:00 |
|
tevador
|
b9d2d853aa
|
Support for multiple threads
|
2018-12-19 21:54:44 +01:00 |
|
tevador
|
cb12feaf91
|
t1ha2 hash for scratchpad digest
|
2018-12-19 12:38:10 +01:00 |
|
tevador
|
ed0bc906d6
|
JIT compiler for x86
|
2018-12-18 22:00:58 +01:00 |
|
tevador
|
ddc29cb4d3
|
Optimized x86 initialization
|
2018-12-16 15:10:03 +01:00 |
|
tevador
|
4f276541d2
|
Modified x86 register allocation
|
2018-12-16 13:43:18 +01:00 |
|
tevador
|
6332831ec1
|
Implemented cache shift
Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
|
2018-12-15 23:13:17 +01:00 |
|
tevador
|
d6ca408ce2
|
Merge branch 'master' of git@github.com:tevador/RandomX.git
|
2018-12-13 23:16:04 +01:00 |
|
tevador
|
cb0721056a
|
Assembly code generator for Windows 64-bit
|
2018-12-13 23:11:55 +01:00 |
Edward Vielmetti
|
8ef8224270
|
update ifdef for _rotr on aarch64
Enables compilation on aarch64 (Packet c1.large.arm)
|
2018-12-12 07:54:33 -05:00 |
|
tevador
|
c9102ee88c
|
RandomX portable interpreter
|
2018-12-11 21:00:30 +01:00 |