mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-08-15 00:23:14 +00:00
Removed optimizable instruction sequences
This commit is contained in:
tevador
parent
2b9209346e
commit
23a357db37
1 changed files with 49 additions and 46 deletions
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@ -143,10 +143,10 @@ namespace RandomX {
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class RegisterInfo {
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public:
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RegisterInfo() : latency(0), lastOpGroup(-1), source(-1), value(0) {}
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RegisterInfo() : latency(0), lastOpGroup(-1), lastOpPar(-1), value(0) {}
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int latency;
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int lastOpGroup;
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int source;
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int lastOpPar;
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int value;
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};
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@ -260,8 +260,8 @@ namespace RandomX {
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class LightInstructionInfo {
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public:
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LightInstructionInfo(const char* name, int type, const MacroOp& op)
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: name_(name), type_(type), latency_(op.getLatency()) {
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LightInstructionInfo(const char* name, int type, const MacroOp& op, int srcOp)
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: name_(name), type_(type), latency_(op.getLatency()), srcOp_(srcOp) {
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ops_.push_back(MacroOp(op));
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}
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template <size_t N>
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@ -334,26 +334,26 @@ namespace RandomX {
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int latency_;
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int resultOp_ = 0;
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int dstOp_ = 0;
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int srcOp_ = 0;
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int srcOp_;
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LightInstructionInfo(const char* name)
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: name_(name), type_(-1), latency_(0) {}
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};
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const LightInstructionInfo LightInstructionInfo::IADD_R = LightInstructionInfo("IADD_R", LightInstructionType::IADD_R, MacroOp::Add_rr);
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const LightInstructionInfo LightInstructionInfo::IADD_C = LightInstructionInfo("IADD_C", LightInstructionType::IADD_C, MacroOp::Add_ri);
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const LightInstructionInfo LightInstructionInfo::IADD_RC = LightInstructionInfo("IADD_RC", LightInstructionType::IADD_RC, MacroOp::Lea_sib);
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const LightInstructionInfo LightInstructionInfo::ISUB_R = LightInstructionInfo("ISUB_R", LightInstructionType::ISUB_R, MacroOp::Sub_rr);
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const LightInstructionInfo LightInstructionInfo::IMUL_9C = LightInstructionInfo("IMUL_9C", LightInstructionType::IMUL_9C, MacroOp::Lea_sib);
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const LightInstructionInfo LightInstructionInfo::IMUL_R = LightInstructionInfo("IMUL_R", LightInstructionType::IMUL_R, MacroOp::Imul_rr);
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const LightInstructionInfo LightInstructionInfo::IMUL_C = LightInstructionInfo("IMUL_C", LightInstructionType::IMUL_C, MacroOp::Imul_rri);
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const LightInstructionInfo LightInstructionInfo::IADD_R = LightInstructionInfo("IADD_R", LightInstructionType::IADD_R, MacroOp::Add_rr, 0);
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const LightInstructionInfo LightInstructionInfo::IADD_C = LightInstructionInfo("IADD_C", LightInstructionType::IADD_C, MacroOp::Add_ri, -1);
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const LightInstructionInfo LightInstructionInfo::IADD_RC = LightInstructionInfo("IADD_RC", LightInstructionType::IADD_RC, MacroOp::Lea_sib, 0);
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const LightInstructionInfo LightInstructionInfo::ISUB_R = LightInstructionInfo("ISUB_R", LightInstructionType::ISUB_R, MacroOp::Sub_rr, 0);
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const LightInstructionInfo LightInstructionInfo::IMUL_9C = LightInstructionInfo("IMUL_9C", LightInstructionType::IMUL_9C, MacroOp::Lea_sib, 0);
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const LightInstructionInfo LightInstructionInfo::IMUL_R = LightInstructionInfo("IMUL_R", LightInstructionType::IMUL_R, MacroOp::Imul_rr, 0);
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const LightInstructionInfo LightInstructionInfo::IMUL_C = LightInstructionInfo("IMUL_C", LightInstructionType::IMUL_C, MacroOp::Imul_rri, -1);
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const LightInstructionInfo LightInstructionInfo::IMULH_R = LightInstructionInfo("IMULH_R", LightInstructionType::IMULH_R, IMULH_R_ops_array, 1, 0, 1);
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const LightInstructionInfo LightInstructionInfo::ISMULH_R = LightInstructionInfo("ISMULH_R", LightInstructionType::ISMULH_R, ISMULH_R_ops_array, 1, 0, 1);
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const LightInstructionInfo LightInstructionInfo::IMUL_RCP = LightInstructionInfo("IMUL_RCP", LightInstructionType::IMUL_RCP, IMUL_RCP_ops_array, 1, 1, -1);
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const LightInstructionInfo LightInstructionInfo::IXOR_R = LightInstructionInfo("IXOR_R", LightInstructionType::IXOR_R, MacroOp::Xor_rr);
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const LightInstructionInfo LightInstructionInfo::IXOR_C = LightInstructionInfo("IXOR_C", LightInstructionType::IXOR_C, MacroOp::Xor_ri);
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const LightInstructionInfo LightInstructionInfo::IXOR_R = LightInstructionInfo("IXOR_R", LightInstructionType::IXOR_R, MacroOp::Xor_rr, 0);
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const LightInstructionInfo LightInstructionInfo::IXOR_C = LightInstructionInfo("IXOR_C", LightInstructionType::IXOR_C, MacroOp::Xor_ri, -1);
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const LightInstructionInfo LightInstructionInfo::IROR_R = LightInstructionInfo("IROR_R", LightInstructionType::IROR_R, IROR_R_ops_array, 1, 1, 0);
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const LightInstructionInfo LightInstructionInfo::IROR_C = LightInstructionInfo("IROR_C", LightInstructionType::IROR_C, MacroOp::Ror_ri);
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const LightInstructionInfo LightInstructionInfo::IROR_C = LightInstructionInfo("IROR_C", LightInstructionType::IROR_C, MacroOp::Ror_ri, -1);
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const LightInstructionInfo LightInstructionInfo::COND_R = LightInstructionInfo("COND_R", LightInstructionType::COND_R, COND_R_ops_array, 5, 5, 3);
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const LightInstructionInfo LightInstructionInfo::NOP = LightInstructionInfo("NOP");
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@ -504,29 +504,28 @@ namespace RandomX {
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IADD_R;
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li.opGroupPar_ = li.src_;
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li.groupParIsSource_ = true;
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} break;
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case LightInstructionType::IADD_C: {
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IADD_R;
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li.opGroupPar_ = li.src_;
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li.groupParIsSource_ = true;
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} break;
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case LightInstructionType::IADD_RC: {
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IADD_R;
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li.opGroupPar_ = li.src_;
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li.groupParIsSource_ = true;
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} break;
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case LightInstructionType::ISUB_R: {
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IADD_R;
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li.opGroupPar_ = li.src_;
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li.groupParIsSource_ = true;
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} break;
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case LightInstructionType::IMUL_9C: {
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@ -544,11 +543,10 @@ namespace RandomX {
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} break;
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case LightInstructionType::IMUL_C: {
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IMUL_C;
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li.opGroupPar_ = li.src_;
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li.opGroupPar_ = -1;
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} break;
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case LightInstructionType::IMULH_R: {
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@ -568,7 +566,6 @@ namespace RandomX {
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} break;
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case LightInstructionType::IMUL_RCP: {
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IMUL_C;
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@ -579,15 +576,14 @@ namespace RandomX {
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IXOR_R;
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li.opGroupPar_ = li.src_;
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li.groupParIsSource_ = true;
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} break;
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case LightInstructionType::IXOR_C: {
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IXOR_R;
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li.opGroupPar_ = li.src_;
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li.opGroupPar_ = -1;
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} break;
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case LightInstructionType::IROR_R: {
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@ -598,9 +594,10 @@ namespace RandomX {
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} break;
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case LightInstructionType::IROR_C: {
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getByte();
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do {
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li.imm32_ = gen.getByte();
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} while ((li.imm32_ & 63) == 0);
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li.opGroup_ = LightInstructionType::IROR_R;
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li.opGroupPar_ = -1;
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} break;
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@ -623,7 +620,7 @@ namespace RandomX {
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bool selectDestination(int cycle, RegisterInfo (®isters)[8], Blake2Generator& gen) {
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std::vector<int> availableRegisters;
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for (unsigned i = 0; i < 8; ++i) {
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if (registers[i].latency <= cycle)
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if (registers[i].latency <= cycle && (canReuse_ || i != src_) && (registers[i].lastOpGroup != opGroup_ || registers[i].lastOpPar != opGroupPar_))
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availableRegisters.push_back(i);
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}
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return selectRegister(availableRegisters, gen, dst_);
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@ -632,10 +629,15 @@ namespace RandomX {
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bool selectSource(int cycle, RegisterInfo(®isters)[8], Blake2Generator& gen) {
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std::vector<int> availableRegisters;
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for (unsigned i = 0; i < 8; ++i) {
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if (registers[i].latency <= cycle && (canReuse_ || i != dst_))
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if (registers[i].latency <= cycle)
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availableRegisters.push_back(i);
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}
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return selectRegister(availableRegisters, gen, src_);
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if (selectRegister(availableRegisters, gen, src_)) {
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if (groupParIsSource_)
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opGroupPar_ = src_;
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return true;
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}
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return false;
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}
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int getType() {
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@ -653,9 +655,6 @@ namespace RandomX {
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int getGroupPar() {
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return opGroupPar_;
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}
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bool hasSource() {
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return hasSource_;
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}
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LightInstructionInfo& getInfo() {
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return info_;
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@ -671,8 +670,8 @@ namespace RandomX {
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uint32_t imm32_;
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int opGroup_;
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int opGroupPar_;
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bool hasSource_ = true;
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bool canReuse_ = false;
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bool groupParIsSource_ = false;
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LightInstruction(const LightInstructionInfo* info) : info_(*info) {
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for (unsigned i = 0; i < info_.getSize(); ++i) {
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@ -818,6 +817,14 @@ namespace RandomX {
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int scheduleCycle = scheduleUop(mop, portBusy, cycle, depCycle);
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mop.setCycle(scheduleCycle);
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if (instrIndex == currentInstruction.getInfo().getSrcOp()) {
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while (!currentInstruction.selectSource(scheduleCycle, registers, gen)) {
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std::cout << "; src STALL at cycle " << cycle << std::endl;
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++scheduleCycle;
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++cycle;
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}
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std::cout << "; src = r" << currentInstruction.getSource() << std::endl;
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}
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if (instrIndex == currentInstruction.getInfo().getDstOp()) {
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while (!currentInstruction.selectDestination(scheduleCycle, registers, gen)) {
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std::cout << "; dst STALL at cycle " << cycle << std::endl;
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@ -826,20 +833,16 @@ namespace RandomX {
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}
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std::cout << "; dst = r" << currentInstruction.getDestination() << std::endl;
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}
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if (currentInstruction.hasSource() && instrIndex == currentInstruction.getInfo().getSrcOp()) {
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while (!currentInstruction.selectSource(scheduleCycle, registers, gen)) {
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std::cout << "; src STALL at cycle " << cycle << std::endl;
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++scheduleCycle;
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++cycle;
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}
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std::cout << "; src = r" << currentInstruction.getSource() << std::endl;
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}
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depCycle = scheduleCycle + mop.getLatency();
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if (instrIndex == currentInstruction.getInfo().getResultOp()) {
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int depCycle = scheduleCycle + mop.getLatency();
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registers[currentInstruction.getDestination()].latency = depCycle;
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int dst = currentInstruction.getDestination();
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RegisterInfo& ri = registers[dst];
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ri.latency = depCycle;
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ri.lastOpGroup = currentInstruction.getGroup();
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ri.lastOpPar = currentInstruction.getGroupPar();
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std::cout << "; RETIRED at cycle " << depCycle << std::endl;
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}
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codeSize += mop.getSize();
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mopIndex++;
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instrIndex++;
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