WIP
This commit is contained in:
tevador
parent
cc70e53bb1
commit
59bbb572c2
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@ -20,6 +20,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#pragma once
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#include "Instruction.hpp"
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#include "configuration.h"
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#include <sstream>
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namespace RandomX {
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@ -78,6 +78,9 @@ namespace RandomX {
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uint32_t getImm32() const {
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return load32(&imm32);
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}
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void setImm32(uint32_t val) {
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return store32(&imm32, val);
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}
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const char* getName() const {
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return names[opcode];
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}
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@ -238,12 +238,7 @@ namespace RandomX {
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emitByte(0xc0 + readReg1);
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memcpy(code + codePos, codeLoopLoad, loopLoadSize);
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codePos += loopLoadSize;
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for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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}
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generateCode(prog);
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emit(REX_MOV_RR);
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emitByte(0xc0 + readReg2);
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emit(REX_XOR_EAX);
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@ -52,6 +52,16 @@ namespace RandomX {
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uint8_t* code;
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int32_t codePos;
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template<class P>
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void generateCode(P& prog) {
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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}
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}
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void generateProgramPrologue(Program&);
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void generateProgramEpilogue(Program&);
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int getConditionRegister();
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@ -0,0 +1,342 @@
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/*
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Copyright (c) 2019 tevador
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This file is part of RandomX.
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RandomX is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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RandomX is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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#include "blake2/blake2.h"
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#include "configuration.h"
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#include "Program.hpp"
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#include "blake2/endian.h";
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#include <iostream>
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namespace RandomX {
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namespace LightInstruction {
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constexpr int IADD_R = 0;
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constexpr int IADD_RC = 1;
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constexpr int ISUB_R = 2;
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constexpr int IMUL_9C = 3;
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constexpr int IMUL_R = 4;
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constexpr int IMULH_R = 5;
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constexpr int ISMULH_R = 6;
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constexpr int IMUL_RCP = 7;
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constexpr int IXOR_R = 8;
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constexpr int IROR_R = 9;
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constexpr int COND_R = 10;
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constexpr int COUNT = 11;
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}
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const int lightInstruction[] = {
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LightInstruction::IADD_RC,
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LightInstruction::IADD_RC,
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LightInstruction::ISUB_R,
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LightInstruction::ISUB_R,
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LightInstruction::IMUL_9C,
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LightInstruction::IMUL_R,
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LightInstruction::IMUL_R,
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LightInstruction::IMUL_R,
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LightInstruction::IMULH_R,
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LightInstruction::ISMULH_R,
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LightInstruction::IMUL_RCP,
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LightInstruction::IXOR_R,
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LightInstruction::IXOR_R,
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LightInstruction::IROR_R,
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LightInstruction::IROR_R,
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LightInstruction::COND_R
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};
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namespace LightInstructionOpcode {
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constexpr int IADD_R = 0;
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constexpr int IADD_RC = RANDOMX_FREQ_IADD_R + RANDOMX_FREQ_IADD_M;
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constexpr int ISUB_R = IADD_RC + RANDOMX_FREQ_IADD_RC;
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constexpr int IMUL_9C = ISUB_R + RANDOMX_FREQ_ISUB_R + RANDOMX_FREQ_ISUB_M;
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constexpr int IMUL_R = IMUL_9C + RANDOMX_FREQ_IMUL_9C;
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constexpr int IMULH_R = IMUL_R + RANDOMX_FREQ_IMUL_R + RANDOMX_FREQ_IMUL_M;
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constexpr int ISMULH_R = IMULH_R + RANDOMX_FREQ_IMULH_R + RANDOMX_FREQ_IMULH_M;
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constexpr int IMUL_RCP = ISMULH_R + RANDOMX_FREQ_ISMULH_R + RANDOMX_FREQ_ISMULH_M;;
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constexpr int IXOR_R = IMUL_RCP + RANDOMX_FREQ_IMUL_RCP + RANDOMX_FREQ_INEG_R;
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constexpr int IROR_R = IXOR_R + RANDOMX_FREQ_IXOR_R + RANDOMX_FREQ_IXOR_M;
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constexpr int COND_R = IROR_R + RANDOMX_FREQ_IROR_R + RANDOMX_FREQ_IROL_R + RANDOMX_FREQ_ISWAP_R + RANDOMX_FREQ_FSWAP_R + RANDOMX_FREQ_FADD_R + RANDOMX_FREQ_FADD_M + RANDOMX_FREQ_FSUB_R + RANDOMX_FREQ_FSUB_M + RANDOMX_FREQ_FSCAL_R + RANDOMX_FREQ_FMUL_R + RANDOMX_FREQ_FDIV_M + RANDOMX_FREQ_FSQRT_R;
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}
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const int lightInstructionOpcode[] = {
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LightInstructionOpcode::IADD_R,
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LightInstructionOpcode::IADD_RC,
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LightInstructionOpcode::ISUB_R,
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LightInstructionOpcode::IMUL_9C,
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LightInstructionOpcode::IMUL_R,
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LightInstructionOpcode::IMULH_R,
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LightInstructionOpcode::ISMULH_R,
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LightInstructionOpcode::IMUL_RCP,
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LightInstructionOpcode::IXOR_R,
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LightInstructionOpcode::IROR_R,
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LightInstructionOpcode::COND_R
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};
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constexpr int ALU_COUNT_MUL = 1;
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constexpr int ALU_COUNT = 4;
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constexpr int LIGHT_OPCODE_BITS = 4;
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constexpr int V4_SRC_INDEX_BITS = 3;
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constexpr int V4_DST_INDEX_BITS = 3;
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static int blakeCounter = 0;
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// If we don't have enough data available, generate more
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static FORCE_INLINE void check_data(size_t& data_index, const size_t bytes_needed, uint8_t* data, const size_t data_size)
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{
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if (data_index + bytes_needed > data_size)
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{
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std::cout << "Calling Blake " << (++blakeCounter) << std::endl;
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blake2b(data, data_size, data, data_size, nullptr, 0);
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data_index = 0;
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}
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}
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void generateLightProgram(LightProgram& prog, const void* seed, int indexRegister) {
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// Source: https://www.agner.org/optimize/instruction_tables.pdf
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const int op_latency[LightInstruction::COUNT] = { 1, 2, 1, 2, 3, 5, 5, 4, 1, 2, 5 };
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// Instruction latencies for theoretical ASIC implementation
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const int asic_op_latency[LightInstruction::COUNT] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
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// Available ALUs for each instruction
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const int op_ALUs[LightInstruction::COUNT] = { ALU_COUNT, ALU_COUNT, ALU_COUNT, ALU_COUNT, ALU_COUNT_MUL, ALU_COUNT_MUL, ALU_COUNT_MUL, ALU_COUNT_MUL, ALU_COUNT, ALU_COUNT, ALU_COUNT };
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uint8_t data[64];
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memset(data, 0, sizeof(data));
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memcpy(data, seed, SeedSize);
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// Set data_index past the last byte in data
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// to trigger full data update with blake hash
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// before we start using it
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size_t data_index = sizeof(data);
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int code_size;
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do {
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uint8_t opcode;
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uint8_t dst_index;
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uint8_t src_index;
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uint32_t imm32 = 0;
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int latency[8];
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int asic_latency[9];
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// Tracks previous instruction and value of the source operand for registers R0-R3 throughout code execution
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// byte 0: current value of the destination register
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// byte 1: instruction opcode
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// byte 2: current value of the source register
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//
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// Registers R4-R8 are constant and are treated as having the same value because when we do
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// the same operation twice with two constant source registers, it can be optimized into a single operation
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uint64_t inst_data[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
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bool alu_busy[RANDOMX_LPROG_LATENCY + 1][ALU_COUNT];
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bool is_rotation[LightInstruction::COUNT];
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bool rotated[8];
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int rotate_count = 0;
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memset(latency, 0, sizeof(latency));
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memset(asic_latency, 0, sizeof(asic_latency));
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memset(alu_busy, 0, sizeof(alu_busy));
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memset(is_rotation, 0, sizeof(is_rotation));
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memset(rotated, 0, sizeof(rotated));
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is_rotation[LightInstruction::IROR_R] = true;
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int num_retries = 0;
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code_size = 0;
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int total_iterations = 0;
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// Generate random code to achieve minimal required latency for our abstract CPU
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// Try to get this latency for all 4 registers
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while (((latency[0] < RANDOMX_LPROG_LATENCY) || (latency[1] < RANDOMX_LPROG_LATENCY) || (latency[2] < RANDOMX_LPROG_LATENCY) || (latency[3] < RANDOMX_LPROG_LATENCY)
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|| (latency[4] < RANDOMX_LPROG_LATENCY) || (latency[5] < RANDOMX_LPROG_LATENCY) || (latency[6] < RANDOMX_LPROG_LATENCY) || (latency[7] < RANDOMX_LPROG_LATENCY)) && (num_retries < 64))
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{
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// Fail-safe to guarantee loop termination
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++total_iterations;
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if (total_iterations > 1024) {
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std::cout << "total_iterations = " << total_iterations << std::endl;
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break;
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}
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check_data(data_index, 1, data, sizeof(data));
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const uint8_t b1 = data[data_index++];
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int instrType = lightInstruction[b1 & ((1 << LIGHT_OPCODE_BITS) - 1)];
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check_data(data_index, 1, data, sizeof(data));
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const uint8_t b2 = data[data_index++];
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dst_index = b2 & ((1 << V4_DST_INDEX_BITS) - 1);
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src_index = (b2 >> (V4_DST_INDEX_BITS)) & ((1 << V4_SRC_INDEX_BITS) - 1);
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const int a = dst_index;
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int b = src_index;
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// Don't do rotation with the same destination twice because it's equal to a single rotation
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if (is_rotation[instrType] && rotated[a])
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{
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continue;
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}
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// Don't do the same instruction (except MUL) with the same source value twice because all other cases can be optimized:
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// 2x IADD_RC(a, b, C) = IADD_RC(a, b*2, C1+C2)
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// 2x ISUB_R(a, b) = ISUB_R(a, 2*b)
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// 2x IMUL_R(a, b) = IMUL_R(a, b*b)
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// 2x IMUL_9C(a, C) = 9 * (9 * a + C1) + C2 = 81 * a + (9 * C1 + C2)
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// 2x IMUL_RCP(a, C) = a * (C * C)
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// 2x IXOR_R = NOP
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// 2x IROR_R(a, b) = IROR_R(a, 2*b)
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if (instrType != LightInstruction::IMULH_R && instrType != LightInstruction::ISMULH_R && ((inst_data[a] & 0xFFFF00) == (instrType << 8) + ((inst_data[b] & 255) << 16)))
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{
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continue;
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}
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if ((instrType == LightInstruction::IADD_RC) || (instrType == LightInstruction::IMUL_9C) || (instrType == LightInstruction::IMUL_RCP) || (instrType == LightInstruction::COND_R) || ((instrType != LightInstruction::IMULH_R) && (instrType != LightInstruction::ISMULH_R) && (a == b)))
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{
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check_data(data_index, 4, data, sizeof(data));
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imm32 = load32(&data[data_index++]);
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}
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// Find which ALU is available (and when) for this instruction
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int next_latency = (latency[a] > latency[b]) ? latency[a] : latency[b];
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int alu_index = -1;
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while (next_latency < RANDOMX_LPROG_LATENCY)
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{
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for (int i = op_ALUs[instrType] - 1; i >= 0; --i)
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{
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if (!alu_busy[next_latency][i])
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{
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// ADD is implemented as two 1-cycle instructions on a real CPU, so do an additional availability check
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if ((instrType == LightInstruction::IADD_RC || instrType == LightInstruction::IMUL_9C || instrType == LightInstruction::IMULH_R || instrType == LightInstruction::ISMULH_R) && alu_busy[next_latency + 1][i])
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{
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continue;
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}
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// Rotation can only start when previous rotation is finished, so do an additional availability check
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if (is_rotation[instrType] && (next_latency < rotate_count * op_latency[instrType]))
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{
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continue;
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}
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alu_index = i;
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break;
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}
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}
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if (alu_index >= 0)
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{
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break;
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}
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++next_latency;
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}
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// Don't generate instructions that leave some register unchanged for more than 15 cycles
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if (next_latency > latency[a] + 15)
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{
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continue;
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}
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next_latency += op_latency[instrType];
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if (next_latency <= RANDOMX_LPROG_LATENCY)
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{
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if (is_rotation[instrType])
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{
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++rotate_count;
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}
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// Mark ALU as busy only for the first cycle when it starts executing the instruction because ALUs are fully pipelined
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alu_busy[next_latency - op_latency[instrType]][alu_index] = true;
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latency[a] = next_latency;
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// ASIC is supposed to have enough ALUs to run as many independent instructions per cycle as possible, so latency calculation for ASIC is simple
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asic_latency[a] = ((asic_latency[a] > asic_latency[b]) ? asic_latency[a] : asic_latency[b]) + asic_op_latency[instrType];
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rotated[a] = is_rotation[instrType];
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inst_data[a] = code_size + (instrType << 8) + ((inst_data[b] & 255) << 16);
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prog(code_size).opcode = lightInstructionOpcode[instrType];
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prog(code_size).dst = dst_index;
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prog(code_size).src = src_index;
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prog(code_size).setImm32(imm32);
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if (instrType == LightInstruction::IADD_RC || instrType == LightInstruction::IMUL_9C || instrType == LightInstruction::IMULH_R || instrType == LightInstruction::ISMULH_R)
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{
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// ADD instruction is implemented as two 1-cycle instructions on a real CPU, so mark ALU as busy for the next cycle too
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alu_busy[next_latency - op_latency[instrType] + 1][alu_index] = true;
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}
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++code_size;
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if (code_size >= RANDOMX_LPROG_MIN_SIZE)
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{
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break;
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}
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}
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else
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{
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++num_retries;
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std::cout << "Retry " << num_retries << " with code_size = " << code_size << ", next_latency = " << next_latency << std::endl;
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}
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}
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// ASIC has more execution resources and can extract as much parallelism from the code as possible
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// We need to add a few more MUL and ROR instructions to achieve minimal required latency for ASIC
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// Get this latency for at least 1 of the 4 registers
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const int prev_code_size = code_size;
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if ((code_size < RANDOMX_LPROG_MAX_SIZE) && (asic_latency[indexRegister] < RANDOMX_LPROG_ASIC_LATENCY))
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{
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int min_idx = indexRegister;
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int max_idx = 0;
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for (int i = 1; i < 8; ++i)
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{
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//if (asic_latency[i] < asic_latency[min_idx]) min_idx = i;
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if (asic_latency[i] > asic_latency[max_idx]) max_idx = i;
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}
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const int pattern[3] = { LightInstruction::IMUL_R, LightInstruction::IROR_R, LightInstruction::IMUL_R };
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const int instrType = pattern[(code_size - prev_code_size) % 3];
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latency[min_idx] = latency[max_idx] + op_latency[instrType];
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asic_latency[min_idx] = asic_latency[max_idx] + asic_op_latency[instrType];
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prog(code_size).opcode = lightInstructionOpcode[instrType];
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prog(code_size).dst = min_idx;
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prog(code_size).src = max_idx;
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++code_size;
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}
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for (int i = 0; i < 8; ++i) {
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std::cout << "Latency " << i << " = " << latency[i] << std::endl;
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}
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std::cout << "Code size = " << code_size << std::endl;
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std::cout << "ALUs:" << std::endl;
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for (int i = 0; i < RANDOMX_LPROG_LATENCY + 1; ++i) {
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for (int j = 0; j < ALU_COUNT; ++j) {
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std::cout << (alu_busy[i][j] ? '*' : '_');
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}
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std::cout << std::endl;
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}
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// There is ~98.15% chance that loop condition is false, so this loop will execute only 1 iteration most of the time
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// It never does more than 4 iterations for all block heights < 10,000,000
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} while ((code_size < RANDOMX_LPROG_MIN_SIZE) || (code_size > RANDOMX_LPROG_MAX_SIZE));
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prog.setSize(code_size);
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}
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}
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@ -0,0 +1,24 @@
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/*
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Copyright (c) 2019 tevador
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||||
|
||||
This file is part of RandomX.
|
||||
|
||||
RandomX is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
RandomX is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with RandomX. If not, see<http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "Program.hpp"
|
||||
|
||||
namespace RandomX {
|
||||
void generateLightProgram(LightProgram& prog, const void* seed, int indexRegister);
|
||||
}
|
||||
|
|
@ -21,7 +21,8 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
|
|||
#include "hashAes1Rx4.hpp"
|
||||
|
||||
namespace RandomX {
|
||||
void Program::print(std::ostream& os) const {
|
||||
template<size_t PROGRAM_SIZE>
|
||||
void ProgramBase::print(std::ostream& os) const {
|
||||
for (int i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
|
||||
auto instr = programBuffer[i];
|
||||
os << instr;
|
||||
|
|
|
|||
|
|
@ -39,11 +39,45 @@ namespace RandomX {
|
|||
uint64_t getEntropy(int i) {
|
||||
return load64(&entropyBuffer[i]);
|
||||
}
|
||||
uint32_t getSize() {
|
||||
return RANDOMX_PROGRAM_SIZE;
|
||||
}
|
||||
private:
|
||||
void print(std::ostream&) const;
|
||||
void print(std::ostream& os) const {
|
||||
for (int i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
|
||||
auto instr = programBuffer[i];
|
||||
os << instr;
|
||||
}
|
||||
}
|
||||
uint64_t entropyBuffer[16];
|
||||
Instruction programBuffer[RANDOMX_PROGRAM_SIZE];
|
||||
};
|
||||
|
||||
class LightProgram {
|
||||
public:
|
||||
Instruction& operator()(int pc) {
|
||||
return programBuffer[pc];
|
||||
}
|
||||
friend std::ostream& operator<<(std::ostream& os, const LightProgram& p) {
|
||||
p.print(os);
|
||||
return os;
|
||||
}
|
||||
uint32_t getSize() {
|
||||
return size;
|
||||
}
|
||||
void setSize(uint32_t val) {
|
||||
size = val;
|
||||
}
|
||||
private:
|
||||
void print(std::ostream& os) const {
|
||||
for (unsigned i = 0; i < size; ++i) {
|
||||
auto instr = programBuffer[i];
|
||||
os << instr;
|
||||
}
|
||||
}
|
||||
Instruction programBuffer[RANDOMX_LPROG_MAX_SIZE];
|
||||
uint32_t size;
|
||||
};
|
||||
|
||||
static_assert(sizeof(Program) % 64 == 0, "Invalid size of class Program");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,6 +37,11 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
|
|||
//Number of random Cache accesses per Dataset block. Minimum is 2.
|
||||
#define RANDOMX_CACHE_ACCESSES 8
|
||||
|
||||
#define RANDOMX_LPROG_LATENCY 168
|
||||
#define RANDOMX_LPROG_ASIC_LATENCY 84
|
||||
#define RANDOMX_LPROG_MIN_SIZE 225
|
||||
#define RANDOMX_LPROG_MAX_SIZE 512
|
||||
|
||||
//Dataset size in bytes. Must be a power of 2.
|
||||
#define RANDOMX_DATASET_SIZE (2ULL * 1024 * 1024 * 1024)
|
||||
|
||||
|
|
|
|||
11
src/main.cpp
11
src/main.cpp
|
|
@ -36,6 +36,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
|
|||
#include "dataset.hpp"
|
||||
#include "Cache.hpp"
|
||||
#include "hashAes1Rx4.hpp"
|
||||
#include "LightProgramGenerator.hpp"
|
||||
|
||||
const uint8_t seed[32] = { 191, 182, 222, 175, 249, 89, 134, 104, 241, 68, 191, 62, 162, 166, 61, 64, 123, 191, 227, 193, 118, 60, 188, 53, 223, 133, 175, 24, 123, 230, 55, 74 };
|
||||
|
||||
|
|
@ -203,7 +204,7 @@ void mine(RandomX::VirtualMachine* vm, std::atomic<uint32_t>& atomicNonce, Atomi
|
|||
}
|
||||
|
||||
int main(int argc, char** argv) {
|
||||
bool softAes, genAsm, miningMode, verificationMode, help, largePages, async, genNative, jit;
|
||||
bool softAes, genAsm, miningMode, verificationMode, help, largePages, async, genNative, jit, genLight;
|
||||
int programCount, threadCount, initThreadCount, epoch;
|
||||
|
||||
readOption("--softAes", argc, argv, softAes);
|
||||
|
|
@ -218,6 +219,14 @@ int main(int argc, char** argv) {
|
|||
readOption("--jit", argc, argv, jit);
|
||||
readOption("--genNative", argc, argv, genNative);
|
||||
readOption("--help", argc, argv, help);
|
||||
readOption("--genLight", argc, argv, genLight);
|
||||
|
||||
if (genLight) {
|
||||
RandomX::LightProgram p;
|
||||
RandomX::generateLightProgram(p, seed, 0);
|
||||
std::cout << p << std::endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (genAsm) {
|
||||
if (softAes)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,441 @@
|
|||
#ifndef VARIANT4_RANDOM_MATH_H
|
||||
#define VARIANT4_RANDOM_MATH_H
|
||||
|
||||
// Register size can be configured to either 32 bit (uint32_t) or 64 bit (uint64_t)
|
||||
typedef uint32_t v4_reg;
|
||||
|
||||
enum V4_Settings
|
||||
{
|
||||
// Generate code with minimal theoretical latency = 45 cycles, which is equivalent to 15 multiplications
|
||||
TOTAL_LATENCY = 15 * 3,
|
||||
|
||||
// Always generate at least 60 instructions
|
||||
NUM_INSTRUCTIONS_MIN = 60,
|
||||
|
||||
// Never generate more than 70 instructions (final RET instruction doesn't count here)
|
||||
NUM_INSTRUCTIONS_MAX = 70,
|
||||
|
||||
// Available ALUs for MUL
|
||||
// Modern CPUs typically have only 1 ALU which can do multiplications
|
||||
ALU_COUNT_MUL = 1,
|
||||
|
||||
// Total available ALUs
|
||||
// Modern CPUs have 4 ALUs, but we use only 3 because random math executes together with other main loop code
|
||||
ALU_COUNT = 3,
|
||||
};
|
||||
|
||||
enum V4_InstructionList
|
||||
{
|
||||
MUL, // a*b
|
||||
ADD, // a+b + C, C is an unsigned 32-bit constant
|
||||
SUB, // a-b
|
||||
ROR, // rotate right "a" by "b & 31" bits
|
||||
ROL, // rotate left "a" by "b & 31" bits
|
||||
XOR, // a^b
|
||||
RET, // finish execution
|
||||
V4_INSTRUCTION_COUNT = RET,
|
||||
};
|
||||
|
||||
// V4_InstructionDefinition is used to generate code from random data
|
||||
// Every random sequence of bytes is a valid code
|
||||
//
|
||||
// There are 9 registers in total:
|
||||
// - 4 variable registers
|
||||
// - 5 constant registers initialized from loop variables
|
||||
// This is why dst_index is 2 bits
|
||||
enum V4_InstructionDefinition
|
||||
{
|
||||
V4_OPCODE_BITS = 3,
|
||||
V4_DST_INDEX_BITS = 2,
|
||||
V4_SRC_INDEX_BITS = 3,
|
||||
};
|
||||
|
||||
struct V4_Instruction
|
||||
{
|
||||
uint8_t opcode;
|
||||
uint8_t dst_index;
|
||||
uint8_t src_index;
|
||||
uint32_t C;
|
||||
};
|
||||
|
||||
#ifndef FORCEINLINE
|
||||
#if defined(__GNUC__)
|
||||
#define FORCEINLINE __attribute__((always_inline)) inline
|
||||
#elif defined(_MSC_VER)
|
||||
#define FORCEINLINE __forceinline
|
||||
#else
|
||||
#define FORCEINLINE inline
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef UNREACHABLE_CODE
|
||||
#if defined(__GNUC__)
|
||||
#define UNREACHABLE_CODE __builtin_unreachable()
|
||||
#elif defined(_MSC_VER)
|
||||
#define UNREACHABLE_CODE __assume(false)
|
||||
#else
|
||||
#define UNREACHABLE_CODE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Random math interpreter's loop is fully unrolled and inlined to achieve 100% branch prediction on CPU:
|
||||
// every switch-case will point to the same destination on every iteration of Cryptonight main loop
|
||||
//
|
||||
// This is about as fast as it can get without using low-level machine code generation
|
||||
static FORCEINLINE void v4_random_math(const struct V4_Instruction* code, v4_reg* r)
|
||||
{
|
||||
enum
|
||||
{
|
||||
REG_BITS = sizeof(v4_reg) * 8,
|
||||
};
|
||||
|
||||
#define V4_EXEC(i) \
|
||||
{ \
|
||||
const struct V4_Instruction* op = code + i; \
|
||||
const v4_reg src = r[op->src_index]; \
|
||||
v4_reg* dst = r + op->dst_index; \
|
||||
switch (op->opcode) \
|
||||
{ \
|
||||
case MUL: \
|
||||
*dst *= src; \
|
||||
break; \
|
||||
case ADD: \
|
||||
*dst += src + op->C; \
|
||||
break; \
|
||||
case SUB: \
|
||||
*dst -= src; \
|
||||
break; \
|
||||
case ROR: \
|
||||
{ \
|
||||
const uint32_t shift = src % REG_BITS; \
|
||||
*dst = (*dst >> shift) | (*dst << ((REG_BITS - shift) % REG_BITS)); \
|
||||
} \
|
||||
break; \
|
||||
case ROL: \
|
||||
{ \
|
||||
const uint32_t shift = src % REG_BITS; \
|
||||
*dst = (*dst << shift) | (*dst >> ((REG_BITS - shift) % REG_BITS)); \
|
||||
} \
|
||||
break; \
|
||||
case XOR: \
|
||||
*dst ^= src; \
|
||||
break; \
|
||||
case RET: \
|
||||
return; \
|
||||
default: \
|
||||
UNREACHABLE_CODE; \
|
||||
break; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define V4_EXEC_10(j) \
|
||||
V4_EXEC(j + 0) \
|
||||
V4_EXEC(j + 1) \
|
||||
V4_EXEC(j + 2) \
|
||||
V4_EXEC(j + 3) \
|
||||
V4_EXEC(j + 4) \
|
||||
V4_EXEC(j + 5) \
|
||||
V4_EXEC(j + 6) \
|
||||
V4_EXEC(j + 7) \
|
||||
V4_EXEC(j + 8) \
|
||||
V4_EXEC(j + 9)
|
||||
|
||||
// Generated program can have 60 + a few more (usually 2-3) instructions to achieve required latency
|
||||
// I've checked all block heights < 10,000,000 and here is the distribution of program sizes:
|
||||
//
|
||||
// 60 27960
|
||||
// 61 105054
|
||||
// 62 2452759
|
||||
// 63 5115997
|
||||
// 64 1022269
|
||||
// 65 1109635
|
||||
// 66 153145
|
||||
// 67 8550
|
||||
// 68 4529
|
||||
// 69 102
|
||||
|
||||
// Unroll 70 instructions here
|
||||
V4_EXEC_10(0); // instructions 0-9
|
||||
V4_EXEC_10(10); // instructions 10-19
|
||||
V4_EXEC_10(20); // instructions 20-29
|
||||
V4_EXEC_10(30); // instructions 30-39
|
||||
V4_EXEC_10(40); // instructions 40-49
|
||||
V4_EXEC_10(50); // instructions 50-59
|
||||
V4_EXEC_10(60); // instructions 60-69
|
||||
|
||||
#undef V4_EXEC_10
|
||||
#undef V4_EXEC
|
||||
}
|
||||
|
||||
// If we don't have enough data available, generate more
|
||||
static FORCEINLINE void check_data(size_t* data_index, const size_t bytes_needed, int8_t* data, const size_t data_size)
|
||||
{
|
||||
if (*data_index + bytes_needed > data_size)
|
||||
{
|
||||
hash_extra_blake(data, data_size, (char*) data);
|
||||
*data_index = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// Generates as many random math operations as possible with given latency and ALU restrictions
|
||||
// "code" array must have space for NUM_INSTRUCTIONS_MAX+1 instructions
|
||||
static inline int v4_random_math_init(struct V4_Instruction* code, const uint64_t height)
|
||||
{
|
||||
// MUL is 3 cycles, 3-way addition and rotations are 2 cycles, SUB/XOR are 1 cycle
|
||||
// These latencies match real-life instruction latencies for Intel CPUs starting from Sandy Bridge and up to Skylake/Coffee lake
|
||||
//
|
||||
// AMD Ryzen has the same latencies except 1-cycle ROR/ROL, so it'll be a bit faster than Intel Sandy Bridge and newer processors
|
||||
// Surprisingly, Intel Nehalem also has 1-cycle ROR/ROL, so it'll also be faster than Intel Sandy Bridge and newer processors
|
||||
// AMD Bulldozer has 4 cycles latency for MUL (slower than Intel) and 1 cycle for ROR/ROL (faster than Intel), so average performance will be the same
|
||||
// Source: https://www.agner.org/optimize/instruction_tables.pdf
|
||||
const int op_latency[V4_INSTRUCTION_COUNT] = { 3, 2, 1, 2, 2, 1 };
|
||||
|
||||
// Instruction latencies for theoretical ASIC implementation
|
||||
const int asic_op_latency[V4_INSTRUCTION_COUNT] = { 3, 1, 1, 1, 1, 1 };
|
||||
|
||||
// Available ALUs for each instruction
|
||||
const int op_ALUs[V4_INSTRUCTION_COUNT] = { ALU_COUNT_MUL, ALU_COUNT, ALU_COUNT, ALU_COUNT, ALU_COUNT, ALU_COUNT };
|
||||
|
||||
int8_t data[32];
|
||||
memset(data, 0, sizeof(data));
|
||||
uint64_t tmp = SWAP64LE(height);
|
||||
memcpy(data, &tmp, sizeof(uint64_t));
|
||||
data[20] = -38; // change seed
|
||||
|
||||
// Set data_index past the last byte in data
|
||||
// to trigger full data update with blake hash
|
||||
// before we start using it
|
||||
size_t data_index = sizeof(data);
|
||||
|
||||
int code_size;
|
||||
|
||||
// There is a small chance (1.8%) that register R8 won't be used in the generated program
|
||||
// So we keep track of it and try again if it's not used
|
||||
bool r8_used;
|
||||
do {
|
||||
int latency[9];
|
||||
int asic_latency[9];
|
||||
|
||||
// Tracks previous instruction and value of the source operand for registers R0-R3 throughout code execution
|
||||
// byte 0: current value of the destination register
|
||||
// byte 1: instruction opcode
|
||||
// byte 2: current value of the source register
|
||||
//
|
||||
// Registers R4-R8 are constant and are treated as having the same value because when we do
|
||||
// the same operation twice with two constant source registers, it can be optimized into a single operation
|
||||
uint32_t inst_data[9] = { 0, 1, 2, 3, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF, 0xFFFFFF };
|
||||
|
||||
bool alu_busy[TOTAL_LATENCY + 1][ALU_COUNT];
|
||||
bool is_rotation[V4_INSTRUCTION_COUNT];
|
||||
bool rotated[4];
|
||||
int rotate_count = 0;
|
||||
|
||||
memset(latency, 0, sizeof(latency));
|
||||
memset(asic_latency, 0, sizeof(asic_latency));
|
||||
memset(alu_busy, 0, sizeof(alu_busy));
|
||||
memset(is_rotation, 0, sizeof(is_rotation));
|
||||
memset(rotated, 0, sizeof(rotated));
|
||||
is_rotation[ROR] = true;
|
||||
is_rotation[ROL] = true;
|
||||
|
||||
int num_retries = 0;
|
||||
code_size = 0;
|
||||
|
||||
int total_iterations = 0;
|
||||
r8_used = false;
|
||||
|
||||
// Generate random code to achieve minimal required latency for our abstract CPU
|
||||
// Try to get this latency for all 4 registers
|
||||
while (((latency[0] < TOTAL_LATENCY) || (latency[1] < TOTAL_LATENCY) || (latency[2] < TOTAL_LATENCY) || (latency[3] < TOTAL_LATENCY)) && (num_retries < 64))
|
||||
{
|
||||
// Fail-safe to guarantee loop termination
|
||||
++total_iterations;
|
||||
if (total_iterations > 256)
|
||||
break;
|
||||
|
||||
check_data(&data_index, 1, data, sizeof(data));
|
||||
|
||||
const uint8_t c = ((uint8_t*)data)[data_index++];
|
||||
|
||||
// MUL = opcodes 0-2
|
||||
// ADD = opcode 3
|
||||
// SUB = opcode 4
|
||||
// ROR/ROL = opcode 5, shift direction is selected randomly
|
||||
// XOR = opcodes 6-7
|
||||
uint8_t opcode = c & ((1 << V4_OPCODE_BITS) - 1);
|
||||
if (opcode == 5)
|
||||
{
|
||||
check_data(&data_index, 1, data, sizeof(data));
|
||||
opcode = (data[data_index++] >= 0) ? ROR : ROL;
|
||||
}
|
||||
else if (opcode >= 6)
|
||||
{
|
||||
opcode = XOR;
|
||||
}
|
||||
else
|
||||
{
|
||||
opcode = (opcode <= 2) ? MUL : (opcode - 2);
|
||||
}
|
||||
|
||||
uint8_t dst_index = (c >> V4_OPCODE_BITS) & ((1 << V4_DST_INDEX_BITS) - 1);
|
||||
uint8_t src_index = (c >> (V4_OPCODE_BITS + V4_DST_INDEX_BITS)) & ((1 << V4_SRC_INDEX_BITS) - 1);
|
||||
|
||||
const int a = dst_index;
|
||||
int b = src_index;
|
||||
|
||||
// Don't do ADD/SUB/XOR with the same register
|
||||
if (((opcode == ADD) || (opcode == SUB) || (opcode == XOR)) && (a == b))
|
||||
{
|
||||
// Use register R8 as source instead
|
||||
b = 8;
|
||||
src_index = 8;
|
||||
}
|
||||
|
||||
// Don't do rotation with the same destination twice because it's equal to a single rotation
|
||||
if (is_rotation[opcode] && rotated[a])
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
// Don't do the same instruction (except MUL) with the same source value twice because all other cases can be optimized:
|
||||
// 2xADD(a, b, C) = ADD(a, b*2, C1+C2), same for SUB and rotations
|
||||
// 2xXOR(a, b) = NOP
|
||||
if ((opcode != MUL) && ((inst_data[a] & 0xFFFF00) == (opcode << 8) + ((inst_data[b] & 255) << 16)))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
// Find which ALU is available (and when) for this instruction
|
||||
int next_latency = (latency[a] > latency[b]) ? latency[a] : latency[b];
|
||||
int alu_index = -1;
|
||||
while (next_latency < TOTAL_LATENCY)
|
||||
{
|
||||
for (int i = op_ALUs[opcode] - 1; i >= 0; --i)
|
||||
{
|
||||
if (!alu_busy[next_latency][i])
|
||||
{
|
||||
// ADD is implemented as two 1-cycle instructions on a real CPU, so do an additional availability check
|
||||
if ((opcode == ADD) && alu_busy[next_latency + 1][i])
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
// Rotation can only start when previous rotation is finished, so do an additional availability check
|
||||
if (is_rotation[opcode] && (next_latency < rotate_count * op_latency[opcode]))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
alu_index = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (alu_index >= 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
++next_latency;
|
||||
}
|
||||
|
||||
// Don't generate instructions that leave some register unchanged for more than 7 cycles
|
||||
if (next_latency > latency[a] + 7)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
next_latency += op_latency[opcode];
|
||||
|
||||
if (next_latency <= TOTAL_LATENCY)
|
||||
{
|
||||
if (is_rotation[opcode])
|
||||
{
|
||||
++rotate_count;
|
||||
}
|
||||
|
||||
// Mark ALU as busy only for the first cycle when it starts executing the instruction because ALUs are fully pipelined
|
||||
alu_busy[next_latency - op_latency[opcode]][alu_index] = true;
|
||||
latency[a] = next_latency;
|
||||
|
||||
// ASIC is supposed to have enough ALUs to run as many independent instructions per cycle as possible, so latency calculation for ASIC is simple
|
||||
asic_latency[a] = ((asic_latency[a] > asic_latency[b]) ? asic_latency[a] : asic_latency[b]) + asic_op_latency[opcode];
|
||||
|
||||
rotated[a] = is_rotation[opcode];
|
||||
|
||||
inst_data[a] = code_size + (opcode << 8) + ((inst_data[b] & 255) << 16);
|
||||
|
||||
code[code_size].opcode = opcode;
|
||||
code[code_size].dst_index = dst_index;
|
||||
code[code_size].src_index = src_index;
|
||||
code[code_size].C = 0;
|
||||
|
||||
if (src_index == 8)
|
||||
{
|
||||
r8_used = true;
|
||||
}
|
||||
|
||||
if (opcode == ADD)
|
||||
{
|
||||
// ADD instruction is implemented as two 1-cycle instructions on a real CPU, so mark ALU as busy for the next cycle too
|
||||
alu_busy[next_latency - op_latency[opcode] + 1][alu_index] = true;
|
||||
|
||||
// ADD instruction requires 4 more random bytes for 32-bit constant "C" in "a = a + b + C"
|
||||
check_data(&data_index, sizeof(uint32_t), data, sizeof(data));
|
||||
uint32_t t;
|
||||
memcpy(&t, data + data_index, sizeof(uint32_t));
|
||||
code[code_size].C = SWAP32LE(t);
|
||||
data_index += sizeof(uint32_t);
|
||||
}
|
||||
|
||||
++code_size;
|
||||
if (code_size >= NUM_INSTRUCTIONS_MIN)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
++num_retries;
|
||||
}
|
||||
}
|
||||
|
||||
// ASIC has more execution resources and can extract as much parallelism from the code as possible
|
||||
// We need to add a few more MUL and ROR instructions to achieve minimal required latency for ASIC
|
||||
// Get this latency for at least 1 of the 4 registers
|
||||
const int prev_code_size = code_size;
|
||||
while ((code_size < NUM_INSTRUCTIONS_MAX) && (asic_latency[0] < TOTAL_LATENCY) && (asic_latency[1] < TOTAL_LATENCY) && (asic_latency[2] < TOTAL_LATENCY) && (asic_latency[3] < TOTAL_LATENCY))
|
||||
{
|
||||
int min_idx = 0;
|
||||
int max_idx = 0;
|
||||
for (int i = 1; i < 4; ++i)
|
||||
{
|
||||
if (asic_latency[i] < asic_latency[min_idx]) min_idx = i;
|
||||
if (asic_latency[i] > asic_latency[max_idx]) max_idx = i;
|
||||
}
|
||||
|
||||
const uint8_t pattern[3] = { ROR, MUL, MUL };
|
||||
const uint8_t opcode = pattern[(code_size - prev_code_size) % 3];
|
||||
latency[min_idx] = latency[max_idx] + op_latency[opcode];
|
||||
asic_latency[min_idx] = asic_latency[max_idx] + asic_op_latency[opcode];
|
||||
|
||||
code[code_size].opcode = opcode;
|
||||
code[code_size].dst_index = min_idx;
|
||||
code[code_size].src_index = max_idx;
|
||||
code[code_size].C = 0;
|
||||
++code_size;
|
||||
}
|
||||
|
||||
// There is ~98.15% chance that loop condition is false, so this loop will execute only 1 iteration most of the time
|
||||
// It never does more than 4 iterations for all block heights < 10,000,000
|
||||
} while (!r8_used || (code_size < NUM_INSTRUCTIONS_MIN) || (code_size > NUM_INSTRUCTIONS_MAX));
|
||||
|
||||
// It's guaranteed that NUM_INSTRUCTIONS_MIN <= code_size <= NUM_INSTRUCTIONS_MAX here
|
||||
// Add final instruction to stop the interpreter
|
||||
code[code_size].opcode = RET;
|
||||
code[code_size].dst_index = 0;
|
||||
code[code_size].src_index = 0;
|
||||
code[code_size].C = 0;
|
||||
|
||||
return code_size;
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue