mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-08-15 00:23:14 +00:00
Operand allocation
This commit is contained in:
tevador
parent
acef5ea0d7
commit
2b9209346e
4 changed files with 128 additions and 106 deletions
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@ -58,21 +58,6 @@ namespace RandomX {
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return minIndex;
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}
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void AssemblyGeneratorX86::generateProgram(Program& prog) {
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for (unsigned i = 0; i < 8; ++i) {
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registerUsage[i] = -1;
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}
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asmCode.str(std::string()); //clear
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for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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asmCode << "randomx_isn_" << i << ":" << std::endl;
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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//asmCode << std::endl;
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}
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}
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void AssemblyGeneratorX86::traceint(Instruction& instr) {
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if (trace) {
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asmCode << "\tpush " << regR[instr.dst] << std::endl;
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@ -21,6 +21,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#include "Instruction.hpp"
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#include "configuration.h"
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#include "common.hpp"
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#include <sstream>
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namespace RandomX {
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@ -32,7 +33,21 @@ namespace RandomX {
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class AssemblyGeneratorX86 {
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public:
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void generateProgram(Program&);
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template<class P>
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void generateProgram(P& prog) {
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for (unsigned i = 0; i < 8; ++i) {
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registerUsage[i] = -1;
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}
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asmCode.str(std::string()); //clear
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for (unsigned i = 0; i < prog.getSize(); ++i) {
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asmCode << "randomx_isn_" << i << ":" << std::endl;
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Instruction& instr = prog(i);
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instr.src %= RegistersCount;
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instr.dst %= RegistersCount;
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generateCode(instr, i);
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//asmCode << std::endl;
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}
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}
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void printCode(std::ostream& os) {
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os << asmCode.rdbuf();
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}
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@ -25,6 +25,7 @@ along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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#include <vector>
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#include <algorithm>
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#include <stdexcept>
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#include <iomanip>
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namespace RandomX {
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// Intel Ivy Bridge reference
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@ -142,11 +143,11 @@ namespace RandomX {
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class RegisterInfo {
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public:
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RegisterInfo() : lastOpGroup(-1), source(-1), value(0), latency(0) {}
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RegisterInfo() : latency(0), lastOpGroup(-1), source(-1), value(0) {}
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int latency;
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int lastOpGroup;
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int source;
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int value;
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int latency;
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};
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class MacroOp {
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@ -264,8 +265,8 @@ namespace RandomX {
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ops_.push_back(MacroOp(op));
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}
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template <size_t N>
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LightInstructionInfo(const char* name, int type, const MacroOp(&arr)[N])
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: name_(name), type_(type), latency_(0) {
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LightInstructionInfo(const char* name, int type, const MacroOp(&arr)[N], int resultOp, int dstOp, int srcOp)
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: name_(name), type_(type), latency_(0), resultOp_(resultOp), dstOp_(dstOp), srcOp_(srcOp) {
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for (unsigned i = 0; i < N; ++i) {
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ops_.push_back(MacroOp(arr[i]));
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latency_ += ops_.back().getLatency();
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@ -273,8 +274,8 @@ namespace RandomX {
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static_assert(N > 1, "Invalid array size");
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}
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template <size_t N>
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LightInstructionInfo(const char* name, int type, const MacroOp*(&arr)[N], int latency)
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: name_(name), type_(type), latency_(latency) {
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LightInstructionInfo(const char* name, int type, const MacroOp*(&arr)[N], int latency, int resultOp, int dstOp, int srcOp)
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: name_(name), type_(type), latency_(latency), resultOp_(resultOp), dstOp_(dstOp), srcOp_(srcOp) {
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for (unsigned i = 0; i < N; ++i) {
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ops_.push_back(MacroOp(arr[i]));
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if (arr[i].isDependent()) {
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@ -301,6 +302,15 @@ namespace RandomX {
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int getType() const {
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return type_;
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}
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int getResultOp() const {
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return resultOp_;
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}
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int getDstOp() const {
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return dstOp_;
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}
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int getSrcOp() const {
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return srcOp_;
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}
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static const LightInstructionInfo IADD_R;
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static const LightInstructionInfo IADD_C;
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static const LightInstructionInfo IADD_RC;
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@ -322,6 +332,9 @@ namespace RandomX {
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int type_;
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std::vector<MacroOp> ops_;
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int latency_;
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int resultOp_ = 0;
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int dstOp_ = 0;
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int srcOp_ = 0;
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LightInstructionInfo(const char* name)
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: name_(name), type_(-1), latency_(0) {}
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@ -334,14 +347,14 @@ namespace RandomX {
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const LightInstructionInfo LightInstructionInfo::IMUL_9C = LightInstructionInfo("IMUL_9C", LightInstructionType::IMUL_9C, MacroOp::Lea_sib);
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const LightInstructionInfo LightInstructionInfo::IMUL_R = LightInstructionInfo("IMUL_R", LightInstructionType::IMUL_R, MacroOp::Imul_rr);
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const LightInstructionInfo LightInstructionInfo::IMUL_C = LightInstructionInfo("IMUL_C", LightInstructionType::IMUL_C, MacroOp::Imul_rri);
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const LightInstructionInfo LightInstructionInfo::IMULH_R = LightInstructionInfo("IMULH_R", LightInstructionType::IMULH_R, IMULH_R_ops_array);
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const LightInstructionInfo LightInstructionInfo::ISMULH_R = LightInstructionInfo("ISMULH_R", LightInstructionType::ISMULH_R, ISMULH_R_ops_array);
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const LightInstructionInfo LightInstructionInfo::IMUL_RCP = LightInstructionInfo("IMUL_RCP", LightInstructionType::IMUL_RCP, IMUL_RCP_ops_array);
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const LightInstructionInfo LightInstructionInfo::IMULH_R = LightInstructionInfo("IMULH_R", LightInstructionType::IMULH_R, IMULH_R_ops_array, 1, 0, 1);
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const LightInstructionInfo LightInstructionInfo::ISMULH_R = LightInstructionInfo("ISMULH_R", LightInstructionType::ISMULH_R, ISMULH_R_ops_array, 1, 0, 1);
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const LightInstructionInfo LightInstructionInfo::IMUL_RCP = LightInstructionInfo("IMUL_RCP", LightInstructionType::IMUL_RCP, IMUL_RCP_ops_array, 1, 1, -1);
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const LightInstructionInfo LightInstructionInfo::IXOR_R = LightInstructionInfo("IXOR_R", LightInstructionType::IXOR_R, MacroOp::Xor_rr);
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const LightInstructionInfo LightInstructionInfo::IXOR_C = LightInstructionInfo("IXOR_C", LightInstructionType::IXOR_C, MacroOp::Xor_ri);
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const LightInstructionInfo LightInstructionInfo::IROR_R = LightInstructionInfo("IROR_R", LightInstructionType::IROR_R, IROR_R_ops_array);
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const LightInstructionInfo LightInstructionInfo::IROR_R = LightInstructionInfo("IROR_R", LightInstructionType::IROR_R, IROR_R_ops_array, 1, 1, 0);
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const LightInstructionInfo LightInstructionInfo::IROR_C = LightInstructionInfo("IROR_C", LightInstructionType::IROR_C, MacroOp::Ror_ri);
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const LightInstructionInfo LightInstructionInfo::COND_R = LightInstructionInfo("COND_R", LightInstructionType::COND_R, COND_R_ops_array);
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const LightInstructionInfo LightInstructionInfo::COND_R = LightInstructionInfo("COND_R", LightInstructionType::COND_R, COND_R_ops_array, 5, 5, 3);
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const LightInstructionInfo LightInstructionInfo::NOP = LightInstructionInfo("NOP");
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const int buffer0[] = { 3, 3, 10 };
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@ -426,75 +439,68 @@ namespace RandomX {
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const LightInstructionInfo* slot_8[] = { &LightInstructionInfo::IADD_RC, &LightInstructionInfo::IMUL_9C };
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const LightInstructionInfo* slot_10 = &LightInstructionInfo::IMUL_RCP;
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template<bool erase>
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static int selectRegister(std::vector<int>& availableRegisters, Blake2Generator& gen) {
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if (availableRegisters.size() == 0)
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throw std::runtime_error("No avialable registers");
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static bool selectRegister(std::vector<int>& availableRegisters, Blake2Generator& gen, int& reg) {
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int index;
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if (availableRegisters.size() == 0)
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return false;
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//throw std::runtime_error("No available registers");
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if (availableRegisters.size() > 1) {
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index = gen.getInt32() % availableRegisters.size();
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}
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else {
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index = 0;
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}
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int select = availableRegisters[index];
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if (erase)
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availableRegisters.erase(availableRegisters.begin() + index);
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return select;
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reg = availableRegisters[index];
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return true;
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}
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class LightInstruction {
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public:
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Instruction toInstr() {
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Instruction instr;
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void toInstr(Instruction& instr) {
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instr.opcode = lightInstructionOpcode[getType()];
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instr.dst = dst_;
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instr.src = src_ >= 0 ? src_ : dst_;
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instr.mod = mod_;
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instr.setImm32(imm32_);
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return instr;
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}
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static LightInstruction createForSlot(Blake2Generator& gen, int slotSize, std::vector<int>& availableRegisters, bool isLast = false, bool isFirst = false) {
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static LightInstruction createForSlot(Blake2Generator& gen, int slotSize, bool isLast = false, bool isFirst = false) {
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switch (slotSize)
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{
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case 3:
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if (isLast) {
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return create(slot_3L[gen.getByte() & 7], availableRegisters, gen);
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return create(slot_3L[gen.getByte() & 7], gen);
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}
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else if (isFirst) {
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return create(slot_3F[gen.getByte() & 3], availableRegisters, gen);
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return create(slot_3F[gen.getByte() & 3], gen);
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}
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else {
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return create(slot_3[gen.getByte() & 3], availableRegisters, gen);
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return create(slot_3[gen.getByte() & 3], gen);
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}
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case 4:
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return create(slot_4[gen.getByte() & 1], availableRegisters, gen);
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return create(slot_4[gen.getByte() & 1], gen);
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case 7:
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if (isLast) {
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return create(slot_7L, availableRegisters, gen);
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return create(slot_7L, gen);
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}
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else {
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return create(slot_7[gen.getByte() & 3], availableRegisters, gen);
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return create(slot_7[gen.getByte() & 3], gen);
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}
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case 8:
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return create(slot_8[gen.getByte() & 1], availableRegisters, gen);
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return create(slot_8[gen.getByte() & 1], gen);
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case 10:
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return create(slot_10, availableRegisters, gen);
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return create(slot_10, gen);
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default:
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break;
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}
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}
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static LightInstruction create(const LightInstructionInfo* info, std::vector<int>& availableRegisters, Blake2Generator& gen) {
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static LightInstruction create(const LightInstructionInfo* info, Blake2Generator& gen) {
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LightInstruction li(info);
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switch (info->getType())
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{
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case LightInstructionType::IADD_R: {
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li.dst_ = gen.getByte() & 7;
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do {
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li.src_ = gen.getByte() & 7;
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} while (li.dst_ == li.src_);
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IADD_R;
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@ -502,8 +508,7 @@ namespace RandomX {
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} break;
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case LightInstructionType::IADD_C: {
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li.dst_ = gen.getByte() & 7;
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li.src_ = -1;
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IADD_R;
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@ -511,10 +516,6 @@ namespace RandomX {
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} break;
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case LightInstructionType::IADD_RC: {
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li.dst_ = gen.getByte() & 7;
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do {
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li.src_ = gen.getByte() & 7;
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} while (li.dst_ == li.src_);
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IADD_R;
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@ -522,10 +523,6 @@ namespace RandomX {
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} break;
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case LightInstructionType::ISUB_R: {
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li.dst_ = gen.getByte() & 7;
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do {
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li.src_ = gen.getByte() & 7;
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} while (li.dst_ == li.src_);
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IADD_R;
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@ -533,10 +530,6 @@ namespace RandomX {
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} break;
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case LightInstructionType::IMUL_9C: {
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li.dst_ = gen.getByte() & 7;
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do {
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li.src_ = gen.getByte() & 7;
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} while (li.dst_ == li.src_);
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IMUL_C;
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@ -544,10 +537,6 @@ namespace RandomX {
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} break;
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case LightInstructionType::IMUL_R: {
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li.dst_ = gen.getByte() & 7;
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do {
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li.src_ = gen.getByte() & 7;
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} while (li.dst_ == li.src_);
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IMUL_R;
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@ -555,8 +544,7 @@ namespace RandomX {
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} break;
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case LightInstructionType::IMUL_C: {
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li.dst_ = gen.getByte() & 7;
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li.src_ = -1;
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IMUL_C;
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@ -564,8 +552,7 @@ namespace RandomX {
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} break;
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case LightInstructionType::IMULH_R: {
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li.dst_ = gen.getByte() & 7;
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li.src_ = gen.getByte() & 7;
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li.canReuse_ = true;
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IMULH_R;
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@ -573,8 +560,7 @@ namespace RandomX {
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} break;
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case LightInstructionType::ISMULH_R: {
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li.dst_ = gen.getByte() & 7;
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li.src_ = gen.getByte() & 7;
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li.canReuse_ = true;
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::ISMULH_R;
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@ -582,8 +568,7 @@ namespace RandomX {
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} break;
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case LightInstructionType::IMUL_RCP: {
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li.dst_ = gen.getByte() & 7;
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li.src_ = -1;
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IMUL_C;
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@ -591,10 +576,6 @@ namespace RandomX {
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} break;
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case LightInstructionType::IXOR_R: {
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li.dst_ = gen.getByte() & 7;
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do {
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li.src_ = gen.getByte() & 7;
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} while (li.dst_ == li.src_);
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IXOR_R;
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@ -602,8 +583,7 @@ namespace RandomX {
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} break;
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case LightInstructionType::IXOR_C: {
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li.dst_ = gen.getByte() & 7;
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li.src_ = -1;
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::IXOR_R;
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@ -611,10 +591,6 @@ namespace RandomX {
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} break;
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case LightInstructionType::IROR_R: {
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li.dst_ = gen.getByte() & 7;
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do {
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li.src_ = gen.getByte() & 7;
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} while (li.dst_ == li.src_);
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li.mod_ = 0;
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li.imm32_ = 0;
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li.opGroup_ = LightInstructionType::IROR_R;
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@ -622,8 +598,7 @@ namespace RandomX {
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} break;
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case LightInstructionType::IROR_C: {
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li.dst_ = gen.getByte() & 7;
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li.src_ = -1;
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li.hasSource_ = false;
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li.mod_ = 0;
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li.imm32_ = gen.getByte();
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li.opGroup_ = LightInstructionType::IROR_R;
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@ -631,8 +606,7 @@ namespace RandomX {
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} break;
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case LightInstructionType::COND_R: {
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li.dst_ = gen.getByte() & 7;
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li.src_ = gen.getByte() & 7;
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li.canReuse_ = true;
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li.mod_ = gen.getByte();
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li.imm32_ = gen.getInt32();
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li.opGroup_ = LightInstructionType::COND_R;
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@ -646,6 +620,24 @@ namespace RandomX {
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return li;
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}
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bool selectDestination(int cycle, RegisterInfo (®isters)[8], Blake2Generator& gen) {
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std::vector<int> availableRegisters;
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for (unsigned i = 0; i < 8; ++i) {
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if (registers[i].latency <= cycle)
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availableRegisters.push_back(i);
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}
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return selectRegister(availableRegisters, gen, dst_);
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}
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bool selectSource(int cycle, RegisterInfo(®isters)[8], Blake2Generator& gen) {
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std::vector<int> availableRegisters;
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for (unsigned i = 0; i < 8; ++i) {
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if (registers[i].latency <= cycle && (canReuse_ || i != dst_))
|
||||
availableRegisters.push_back(i);
|
||||
}
|
||||
return selectRegister(availableRegisters, gen, src_);
|
||||
}
|
||||
|
||||
int getType() {
|
||||
return info_.getType();
|
||||
}
|
||||
|
|
@ -661,6 +653,9 @@ namespace RandomX {
|
|||
int getGroupPar() {
|
||||
return opGroupPar_;
|
||||
}
|
||||
bool hasSource() {
|
||||
return hasSource_;
|
||||
}
|
||||
|
||||
LightInstructionInfo& getInfo() {
|
||||
return info_;
|
||||
|
|
@ -670,12 +665,14 @@ namespace RandomX {
|
|||
|
||||
private:
|
||||
LightInstructionInfo info_;
|
||||
int src_;
|
||||
int dst_;
|
||||
int src_ = -1;
|
||||
int dst_ = -1;
|
||||
int mod_;
|
||||
uint32_t imm32_;
|
||||
int opGroup_;
|
||||
int opGroupPar_;
|
||||
bool hasSource_ = true;
|
||||
bool canReuse_ = false;
|
||||
|
||||
LightInstruction(const LightInstructionInfo* info) : info_(*info) {
|
||||
for (unsigned i = 0; i < info_.getSize(); ++i) {
|
||||
|
|
@ -782,7 +779,6 @@ namespace RandomX {
|
|||
RegisterInfo registers[8];
|
||||
Blake2Generator gen(seed);
|
||||
std::vector<LightInstruction> instructions;
|
||||
std::vector<int> availableRegisters;
|
||||
|
||||
DecoderBuffer& fetchLine = DecoderBuffer::Default;
|
||||
LightInstruction currentInstruction = LightInstruction::Null;
|
||||
|
|
@ -794,22 +790,20 @@ namespace RandomX {
|
|||
int depCycle = 0;
|
||||
int mopIndex = 0;
|
||||
bool portsSaturated = false;
|
||||
int outIndex = 0;
|
||||
|
||||
while(!portsSaturated) {
|
||||
fetchLine = fetchLine.fetchNext(currentInstruction.getType(), gen);
|
||||
std::cout << "; ------------- fetch cycle " << cycle << " (" << fetchLine.getName() << ")" << std::endl;
|
||||
|
||||
availableRegisters.clear();
|
||||
for (unsigned i = 0; i < 8; ++i) {
|
||||
if (registers[i].latency <= cycle)
|
||||
availableRegisters.push_back(i);
|
||||
}
|
||||
|
||||
mopIndex = 0;
|
||||
|
||||
while (!portsSaturated && mopIndex < fetchLine.getSize()) {
|
||||
if (instrIndex >= currentInstruction.getInfo().getSize()) {
|
||||
currentInstruction = LightInstruction::createForSlot(gen, fetchLine.getCounts()[mopIndex], availableRegisters, fetchLine.getSize() == mopIndex + 1, fetchLine.getIndex() == 0 && mopIndex == 0);
|
||||
if (currentInstruction.getType() >= 0) {
|
||||
currentInstruction.toInstr(prog(outIndex++));
|
||||
}
|
||||
currentInstruction = LightInstruction::createForSlot(gen, fetchLine.getCounts()[mopIndex], fetchLine.getSize() == mopIndex + 1, fetchLine.getIndex() == 0 && mopIndex == 0);
|
||||
instrIndex = 0;
|
||||
std::cout << "; " << currentInstruction.getInfo().getName() << std::endl;
|
||||
rxOpCount++;
|
||||
|
|
@ -821,16 +815,38 @@ namespace RandomX {
|
|||
}
|
||||
|
||||
std::cout << mop.getName() << " ";
|
||||
int scheduleCycle = scheduleUop(mop, portBusy, cycle, depCycle);
|
||||
mop.setCycle(scheduleCycle);
|
||||
|
||||
if (instrIndex == currentInstruction.getInfo().getDstOp()) {
|
||||
while (!currentInstruction.selectDestination(scheduleCycle, registers, gen)) {
|
||||
std::cout << "; dst STALL at cycle " << cycle << std::endl;
|
||||
++scheduleCycle;
|
||||
++cycle;
|
||||
}
|
||||
std::cout << "; dst = r" << currentInstruction.getDestination() << std::endl;
|
||||
}
|
||||
if (currentInstruction.hasSource() && instrIndex == currentInstruction.getInfo().getSrcOp()) {
|
||||
while (!currentInstruction.selectSource(scheduleCycle, registers, gen)) {
|
||||
std::cout << "; src STALL at cycle " << cycle << std::endl;
|
||||
++scheduleCycle;
|
||||
++cycle;
|
||||
}
|
||||
std::cout << "; src = r" << currentInstruction.getSource() << std::endl;
|
||||
}
|
||||
if (instrIndex == currentInstruction.getInfo().getResultOp()) {
|
||||
int depCycle = scheduleCycle + mop.getLatency();
|
||||
registers[currentInstruction.getDestination()].latency = depCycle;
|
||||
std::cout << "; RETIRED at cycle " << depCycle << std::endl;
|
||||
}
|
||||
|
||||
codeSize += mop.getSize();
|
||||
mopIndex++;
|
||||
instrIndex++;
|
||||
macroOpCount++;
|
||||
int scheduleCycle = scheduleUop(mop, portBusy, cycle, depCycle);
|
||||
if (scheduleCycle >= RANDOMX_LPROG_LATENCY) {
|
||||
portsSaturated = true;
|
||||
}
|
||||
mop.setCycle(scheduleCycle);
|
||||
depCycle = scheduleCycle + mop.getLatency();
|
||||
}
|
||||
++cycle;
|
||||
}
|
||||
|
|
@ -857,11 +873,14 @@ namespace RandomX {
|
|||
std::cout << "; RandomX instructions: " << rxOpCount << std::endl;
|
||||
|
||||
for (int i = 0; i < RANDOMX_LPROG_LATENCY + 1; ++i) {
|
||||
std::cout << std::setw(3) << i << " ";
|
||||
for (int j = 0; j < 3; ++j) {
|
||||
std::cout << (portBusy[i][j] ? '*' : '_');
|
||||
}
|
||||
std::cout << std::endl;
|
||||
}
|
||||
|
||||
prog.setSize(outIndex);
|
||||
}
|
||||
|
||||
void generateLightProgram(LightProgram& prog, const void* seed, int indexRegister) {
|
||||
|
|
|
|||
|
|
@ -224,7 +224,10 @@ int main(int argc, char** argv) {
|
|||
if (genLight) {
|
||||
RandomX::LightProgram p;
|
||||
RandomX::generateLightProg2(p, seed, 0);
|
||||
//std::cout << p << std::endl;
|
||||
RandomX::AssemblyGeneratorX86 asmX86;
|
||||
asmX86.generateProgram(p);
|
||||
std::cout << "-------------------------------------------------------" << std::endl;
|
||||
asmX86.printCode(std::cout);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue