tevador
b4c02051fa
Reworked SuperscalarHash instruction set
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ASM and C code generator for SuperscalarHash
Support for Superscalar hash in the light mode
2019-04-07 15:38:51 +02:00
tevador
77dbe14658
SuperscalarHash JIT compiler
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(unfinished)
2019-04-06 12:00:56 +02:00
tevador
690707ef49
Reworked addition instructions
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Some bug fixes
2019-04-03 14:06:59 +02:00
tevador
2aaec84931
Bug fixes, trace output
2019-04-03 09:53:25 +02:00
tevador
428b845a3d
Fixed an infinite loop bug
2019-04-01 19:04:08 +02:00
tevador
2b9209346e
Operand allocation
2019-04-01 00:38:17 +02:00
tevador
2fd0a125b5
Front-end simulation
2019-03-31 13:32:16 +02:00
tevador
59bbb572c2
WIP
2019-03-28 15:27:10 +01:00
tevador
107270d93d
Reduced Dataset size to 2 GiB with 8 memory accesses per block
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Disabled Dataset growth
2019-03-22 12:53:16 +01:00
tevador
4c1ae951de
Merge branch 'feature/branches' into dev
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Conflicts:
src/JitCompilerX86.cpp
src/JitCompilerX86.hpp
src/main.cpp
2019-03-22 11:53:48 +01:00
tevador
73a11f5c01
CompiledLightVirtualMachine
2019-03-21 20:44:59 +01:00
tevador
007f8599b9
Implemented branches in the interpreter
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Fixed x86 immediate encoding
2019-03-20 23:38:37 +01:00
tevador
91063aac91
Reference result
2019-03-16 20:59:42 +01:00
tevador
2edf05cedc
Implemented Dataset size increase per epoch
2019-03-10 23:14:03 +01:00
tevador
e65d9da66c
Configurable parameters separated into configuration.h
2019-03-08 15:34:34 +01:00
tevador
096a7c0d7b
Implemented virtual memory free
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Removed legacy AES code
2019-03-08 11:46:03 +01:00
tevador
7c012b4fee
Fixed non-portable nonce serialization
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updated program.inc
2019-02-25 09:31:35 +01:00
tevador
d9bc6cfeda
Updated JIT compiler and assembly generator for new int -> float conversion
2019-02-24 17:24:06 +01:00
tevador
f3b114af88
Replaced division instructions with IMUL_RCP
2019-02-22 17:48:26 +01:00
tevador
219efce06c
New command line options
2019-02-19 22:47:45 +01:00
tevador
bfd557dac5
Added reference result
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Fixed undefined initial rounding mode
2019-02-17 10:54:51 +01:00
tevador
923420f0a3
Fixed mining and verification mode not giving the same results
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Trace support in Assembly generator
2019-02-16 23:18:45 +01:00
tevador
a145caa185
Fixed JIT compiler not producing the same code as genAsm and genNative
2019-02-15 16:43:52 +01:00
tevador
447e8a1d4f
Simplified division in interpreted mode
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Fixed incorrect condition code in JitCompilerX86
Refactoring
2019-02-15 10:41:02 +01:00
tevador
1df975e583
Restored software AES support
2019-02-13 22:46:32 +01:00
tevador
0b1761a846
Refactoring: mining/verification mode
2019-02-11 18:57:42 +01:00
tevador
b8ce504be6
Added comments to hashAes1Rx4 and fillAes1Rx4
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Fixed gcc compilation
Added performance numbers
2019-02-09 19:32:53 +01:00
tevador
2798d78717
Render imm32 as signed in RandomX code
2019-02-09 16:19:15 +01:00
tevador
32d827d0a6
Interpreter with bytecode
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Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
2019-02-09 15:45:26 +01:00
tevador
b417fd08ea
16 -> 8 chained programs
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constant address loads are always from L3
2019-02-05 23:06:44 +01:00
tevador
1ee94bef2a
Added ISWAP instruction
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Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
2019-02-04 17:07:00 +01:00
tevador
8f2abd6c05
NOP instruction
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register load/store from L3
2019-01-27 18:19:49 +01:00
tevador
005c67f64c
Added explicit STORE instructions
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JIT compiler
2019-01-27 10:52:30 +01:00
tevador
d2cb086221
ASM code generator for "small" programs that fit into the uOP cache
2019-01-24 19:29:59 +01:00
tevador
bd0dba88a8
4 scratchpad segments
2019-01-20 00:44:01 +01:00
tevador
16db607025
Scratchpad size increased to 1 MiB
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New AES-based scratchpad hashing function
2019-01-18 23:51:18 +01:00
tevador
93c324709b
Related to previous changes
2019-01-18 19:06:46 +01:00
tevador
4fb168e249
Large page support for cache
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Bug fixes
2019-01-18 17:57:47 +01:00
tevador
8b1102ee05
Interpreter + async mode
2019-01-15 00:01:11 +01:00
tevador
1426fcbab5
Print average program code size
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Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
2019-01-12 16:05:09 +01:00
tevador
d1a808643d
Random accesses - JIT compiler
2019-01-10 22:04:55 +01:00
tevador
619bee5418
Random dataset accesses - asm only
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Initial support for large pages
2019-01-04 19:44:15 +01:00
tevador
3caecc7646
Vector FPU instructions
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JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
2018-12-31 19:06:45 +01:00
tevador
5bc26348f1
Updated readme with performance data
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Added --help option
2018-12-23 18:02:17 +01:00
tevador
03913d0e81
Run a single thread synchronously
2018-12-23 15:12:54 +01:00
tevador
740c40b218
8 branch conditions for CALL/RET
2018-12-21 22:41:35 +01:00
tevador
55afe9646f
Debuggable assembly generator
2018-12-21 21:09:55 +01:00
tevador
b9d2d853aa
Support for multiple threads
2018-12-19 21:54:44 +01:00
tevador
cb12feaf91
t1ha2 hash for scratchpad digest
2018-12-19 12:38:10 +01:00
tevador
ed0bc906d6
JIT compiler for x86
2018-12-18 22:00:58 +01:00