tevador
91cd35ff13
Decrease the frequency of FADD/FSUB in favor of FMUL ( #77 )
...
* this better matches CPU capabilities since execution ports are usually split 1:1 between fadd and fmul
* the frequency of FSWAP_R decreased from 8 to 4 (it's ASIC-friendly)
* activate IROL_R instruction
2019-06-22 16:05:22 +02:00
tevador
0c5b666df4
Configuration guidelines ( #59 )
...
* added detailed guidelines for the selection of configuration values
* added additional compile-time checks to prevent bad configurations
* removed RANDOMX_SUPERSCALAR_MAX_SIZE parameter
2019-06-10 15:57:36 +02:00
tevador
2706a8b753
Relicensed under the 3-clause BSD license
2019-05-18 14:21:47 +02:00
tevador
c1314dc2a2
Use values from configuration.h in assembly code
2019-05-06 18:14:00 +02:00
tevador
9e5eac8645
Fixed a chance of CBRANCH looping
...
Fixed CBRANCH jump probability being lower than expected
2019-05-03 14:02:40 +02:00
tevador
be21ba767c
Doubled the frequency of CBRANCH, halved the jumping probability
2019-04-30 14:09:46 +02:00
tevador
ffebc37381
COND_R instruction reworked as CBRANCH
...
instruction mod field bits reallocated
2019-04-29 23:38:23 +02:00
tevador
7f6bdd9a52
Code cleanup & refactoring
2019-04-28 16:42:45 +02:00
tevador
fd7186f873
Changed IADD_RS to use mod.mem
2019-04-27 23:52:26 +02:00
tevador
270a4f97fe
Dataset size increased to 2080 MiB
...
Implemented dataset base offset
Tweaked SuperscalarHash constants to prevent register collisions
2019-04-26 16:05:30 +02:00
tevador
f66da3911e
Fixed some compilation issues
...
Code cleanup
2019-04-26 11:07:47 +02:00
tevador
4c66b2305a
Formatting & refactoring
2019-04-22 18:20:46 +02:00
tevador
41b51a4858
Cleaned up legacy code
2019-04-21 14:07:32 +02:00
tevador
682000b1a9
Unique scratchpad addresses - interpreter
...
Additional writes to L3
2019-04-16 18:58:44 +02:00
tevador
24a22c6b54
Code generator refactoring
2019-04-12 00:02:22 +02:00
tevador
6e3136b37f
Fixed cache alignment
...
Performance tuning
2019-04-06 17:07:40 +02:00
tevador
77dbe14658
SuperscalarHash JIT compiler
...
(unfinished)
2019-04-06 12:00:56 +02:00
tevador
59bbb572c2
WIP
2019-03-28 15:27:10 +01:00
tevador
2bb42637fd
Epoch increased to 2048 blocks
2019-03-22 14:03:13 +01:00
tevador
107270d93d
Reduced Dataset size to 2 GiB with 8 memory accesses per block
...
Disabled Dataset growth
2019-03-22 12:53:16 +01:00
tevador
174754cb2b
Added branches - ASM and JIT only
2019-03-17 23:09:11 +01:00
tevador
a1dc094c19
added epoch lag configuration
2019-03-11 23:43:52 +01:00
tevador
2edf05cedc
Implemented Dataset size increase per epoch
2019-03-10 23:14:03 +01:00
tevador
e65d9da66c
Configurable parameters separated into configuration.h
2019-03-08 15:34:34 +01:00