tevador
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5b7df0c5e1
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Test ASM for a new program structure
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2019-01-24 19:35:11 +01:00 |
tevador
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d2cb086221
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ASM code generator for "small" programs that fit into the uOP cache
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2019-01-24 19:29:59 +01:00 |
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tevador
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bd0dba88a8
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4 scratchpad segments
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2019-01-20 00:44:01 +01:00 |
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tevador
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16db607025
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Scratchpad size increased to 1 MiB
New AES-based scratchpad hashing function
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2019-01-18 23:51:18 +01:00 |
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tevador
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93c324709b
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Related to previous changes
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2019-01-18 19:06:46 +01:00 |
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tevador
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89bc68d093
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Memory-bound dataset initialization
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2019-01-18 18:44:06 +01:00 |
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tevador
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4fb168e249
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Large page support for cache
Bug fixes
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2019-01-18 17:57:47 +01:00 |
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tevador
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8b1102ee05
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Interpreter + async mode
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2019-01-15 00:01:11 +01:00 |
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tevador
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c2e0122e15
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Comparison with CryptoNight
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2019-01-13 23:51:12 +01:00 |
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tevador
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a7ffe8c19a
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Mix dataset cacheline with registers r0-r7
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2019-01-13 21:14:59 +01:00 |
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tevador
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48d85643de
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Dataset intialization algorithm (AES)
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2019-01-13 13:47:25 +01:00 |
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tevador
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67e741ff22
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Reduced x86 code size by 512 bytes (and ecx -> and eax)
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2019-01-12 20:27:35 +01:00 |
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tevador
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1426fcbab5
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Print average program code size
Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
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2019-01-12 16:05:09 +01:00 |
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tevador
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2756bcdcfe
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Added magic division to JIT compiler
New B operand selection rules
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2019-01-11 16:53:52 +01:00 |
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tevador
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451dfc5730
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Optimized division by constants
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2019-01-11 14:08:21 +01:00 |
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tevador
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c02ee4291d
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FPROUND - variable flag offset
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2019-01-11 10:52:12 +01:00 |
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tevador
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e487092f07
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Simplified CALL and RET
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2019-01-11 10:18:24 +01:00 |
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tevador
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557241cd95
|
JUMP instruction
|
2019-01-11 09:58:06 +01:00 |
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tevador
|
6941b2cb69
|
Reworked instruction set documentation
|
2019-01-10 23:36:53 +01:00 |
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tevador
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d1a808643d
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Random accesses - JIT compiler
|
2019-01-10 22:04:55 +01:00 |
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tevador
|
b71e0eec65
|
Optimizations to reduce code size under 32K
|
2019-01-08 14:50:31 +01:00 |
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tevador
|
b6d654291f
|
90 address transformations
|
2019-01-08 12:19:19 +01:00 |
|
tevador
|
2f6a599ff6
|
Inlined calls for memory read
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2019-01-07 17:44:43 +01:00 |
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tevador
|
6519fed4d1
|
Combined prefetch + read into a single step
|
2019-01-07 11:26:43 +01:00 |
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tevador
|
4189e4ebc6
|
Original number of VM instructions
|
2019-01-06 17:23:05 +01:00 |
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tevador
|
619bee5418
|
Random dataset accesses - asm only
Initial support for large pages
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2019-01-04 19:44:15 +01:00 |
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tevador
|
bf8397b08d
|
Updated specification
|
2018-12-31 19:27:31 +01:00 |
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tevador
|
3caecc7646
|
Vector FPU instructions
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
|
2018-12-31 19:06:45 +01:00 |
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tevador
|
a09bee8d60
|
js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up)
|
2018-12-28 14:18:41 +01:00 |
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tevador
|
76b6b05cf2
|
Unconditional RET
|
2018-12-28 12:09:37 +01:00 |
|
tevador
|
39c569ae44
|
Fixed a potential crash in JitCompilerX86
|
2018-12-27 21:42:38 +01:00 |
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tevador
|
5bc26348f1
|
Updated readme with performance data
Added --help option
|
2018-12-23 18:02:17 +01:00 |
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tevador
|
03913d0e81
|
Run a single thread synchronously
|
2018-12-23 15:12:54 +01:00 |
|
tevador
|
c05947db09
|
Bug fixes
|
2018-12-23 14:25:22 +01:00 |
|
tevador
|
ca59925495
|
JitCompilerX86: use mmap to allocate an executable buffer
compile as c++11
|
2018-12-23 14:09:09 +01:00 |
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tevador
|
740c40b218
|
8 branch conditions for CALL/RET
|
2018-12-21 22:41:35 +01:00 |
|
tevador
|
55afe9646f
|
Debuggable assembly generator
|
2018-12-21 21:09:55 +01:00 |
|
tevador
|
fce6e75689
|
Fixed copyright notice
|
2018-12-21 21:04:35 +01:00 |
|
tevador
|
ffa67295c4
|
Instruction statistics
|
2018-12-20 22:42:47 +01:00 |
|
tevador
|
1db7dd6e8b
|
Renamed immediate constants
|
2018-12-20 18:36:09 +01:00 |
|
tevador
|
b9d2d853aa
|
Support for multiple threads
|
2018-12-19 21:54:44 +01:00 |
|
tevador
|
cb12feaf91
|
t1ha2 hash for scratchpad digest
|
2018-12-19 12:38:10 +01:00 |
|
tevador
|
ed0bc906d6
|
JIT compiler for x86
|
2018-12-18 22:00:58 +01:00 |
|
tevador
|
ddc29cb4d3
|
Optimized x86 initialization
|
2018-12-16 15:10:03 +01:00 |
|
tevador
|
4f276541d2
|
Modified x86 register allocation
|
2018-12-16 13:43:18 +01:00 |
|
tevador
|
6332831ec1
|
Implemented cache shift
Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
|
2018-12-15 23:13:17 +01:00 |
|
tevador
|
4fc4b840f5
|
Updated documentation
|
2018-12-14 12:12:18 +01:00 |
|
tevador
|
d6ca408ce2
|
Merge branch 'master' of git@github.com:tevador/RandomX.git
|
2018-12-13 23:16:04 +01:00 |
|
tevador
|
cb0721056a
|
Assembly code generator for Windows 64-bit
|
2018-12-13 23:11:55 +01:00 |
|
tevador
|
52beccc309
|
Merge pull request #6 from vielmetti/patch-1
update ifdef for _rotr on aarch64
|
2018-12-12 16:46:39 +01:00 |