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Reworked instruction set documentation
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# RandomX instruction listing
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There are 31 unique instructions divided into 3 groups:
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|group|# operations|# opcodes||
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|---------|-----------------|----|-|
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|integer (IA)|22|144|56.3%|
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|floating point (FP)|5|76|29.7%|
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|control (CL)|4|36|14.0%
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||**31**|**256**|**100%**
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## Integer instructions
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There are 22 integer instructions. They are divided into 3 classes (MATH, DIV, SHIFT) with different B operand selection rules.
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|# opcodes|instruction|class|signed|A width|B width|C|C width|
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|-|-|-|-|-|-|-|-|
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|12|ADD_64|MATH|no|64|64|`A + B`|64|
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|2|ADD_32|MATH|no|32|32|`A + B`|32|
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|12|SUB_64|MATH|no|64|64|`A - B`|64|
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|2|SUB_32|MATH|no|32|32|`A - B`|32|
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|21|MUL_64|MATH|no|64|64|`A * B`|64|
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|10|MULH_64|MATH|no|64|64|`A * B`|64|
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|15|MUL_32|MATH|no|32|32|`A * B`|64|
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|15|IMUL_32|MATH|yes|32|32|`A * B`|64|
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|10|IMULH_64|MATH|yes|64|64|`A * B`|64|
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|4|DIV_64|DIV|no|64|32|`A / B`|64|
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|4|IDIV_64|DIV|yes|64|32|`A / B`|64|
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|4|AND_64|MATH|no|64|64|`A & B`|64|
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|2|AND_32|MATH|no|32|32|`A & B`|32|
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|4|OR_64|MATH|no|64|64|`A | B`|64|
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|2|OR_32|MATH|no|32|32|`A | B`|32|
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|4|XOR_64|MATH|no|64|64|`A ^ B`|64|
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|2|XOR_32|MATH|no|32|32|`A ^ B`|32|
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|3|SHL_64|SHIFT|no|64|6|`A << B`|64|
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|3|SHR_64|SHIFT|no|64|6|`A >> B`|64|
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|3|SAR_64|SHIFT|yes|64|6|`A >> B`|64|
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|6|ROL_64|SHIFT|no|64|6|`A <<< B`|64|
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|6|ROR_64|SHIFT|no|64|6|`A >>> B`|64|
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#### 32-bit operations
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Instructions ADD_32, SUB_32, AND_32, OR_32, XOR_32 only use the low-order 32 bits of the input operands. The result of these operations is 32 bits long and bits 32-63 of C are set to zero.
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#### Multiplication
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There are 5 different multiplication operations. MUL_64 and MULH_64 both take 64-bit unsigned operands, but MUL_64 produces the low 64 bits of the result and MULH_64 produces the high 64 bits. MUL_32 and IMUL_32 use only the low-order 32 bits of the operands and produce a 64-bit result. The signed variant interprets the arguments as signed integers. IMULH_64 takes two 64-bit signed operands and produces the high-order 64 bits of the result.
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#### Division
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For the division instructions, the dividend is 64 bits long and the divisor 32 bits long. The IDIV_64 instruction interprets both operands as signed integers. In case of division by zero or signed overflow, the result is equal to the dividend `A`.
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75% of division instructions use a runtime-constant divisor and can be optimized using a multiplication and shifts.
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#### Shift and rotate
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The shift/rotate instructions use just the bottom 6 bits of the `B` operand (`imm8` is used as the immediate value). All treat `A` as unsigned except SAR_64, which performs an arithmetic right shift by copying the sign bit.
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## Floating point instructions
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There are 5 floating point instructions. All floating point instructions are vector instructions that operate on two packed double precision floating point values.
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|# opcodes|instruction|C|
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|-|-|-|-|
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|20|FPADD|`A + B`|
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|20|FPSUB|`A - B`|
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|22|FPMUL|`A * B`|
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|8|FPDIV|`A / B`|
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|6|FPSQRT|`sqrt(abs(A))`|
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#### Conversion of operand A
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Operand A is loaded from memory as a 64-bit value. All floating point instructions interpret A as two packed 32-bit signed integers and convert them into two packed double precision floating point values.
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#### Rounding
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FPU instructions conform to the IEEE-754 specification, so they must give correctly rounded results. Initial rounding mode is *roundTiesToEven*. Rounding mode can be changed by the `FPROUND` control instruction. Denormal values must be always flushed to zero.
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#### NaN
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If an operation produces NaN, the result is converted into positive zero. NaN results may never be written into registers or memory. Only division and multiplication must be checked for NaN results (`0.0 / 0.0` and `0.0 * Infinity` result in NaN).
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## Control instructions
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There are 4 control instructions.
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|# opcodes|instruction|description|condition|
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|-|-|-|-|
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|2|FPROUND|change floating point rounding mode|-
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|11|JUMP|conditional jump|(see condition table below)
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|11|CALL|conditional procedure call|(see condition table below)
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|12|RET|return from procedure|stack is not empty
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All control instructions behave as 'arithmetic no-op' and simply copy the input operand A into the destination C.
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The JUMP and CALL instructions use a condition function, which takes the lower 32 bits of operand B (register) and the value `imm32` and evaluates a condition based on the `B.LOC.C` flag:
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|`B.LOC.C`|signed|jump condition|probability|*x86*|*ARM*
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|---|---|----------|-----|--|----|
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|0|no|`B <= imm32`|0% - 100%|`JBE`|`BLS`
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|1|no|`B > imm32`|0% - 100%|`JA`|`BHI`
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|2|yes|`B - imm32 < 0`|50%|`JS`|`BMI`
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|3|yes|`B - imm32 >= 0`|50%|`JNS`|`BPL`
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|4|yes|`B - imm32` overflows|0% - 50%|`JO`|`BVS`
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|5|yes|`B - imm32` doesn't overflow|50% - 100%|`JNO`|`BVC`
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|6|yes|`B < imm32`|0% - 100%|`JL`|`BLT`
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|7|yes|`B >= imm32`|0% - 100%|`JGE`|`BGE`
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The 'signed' column specifies if the operands are interpreted as signed or unsigned 32-bit numbers. Column 'probability' lists the expected jump probability (range means that the actual value for a specific instruction depends on `imm32`). *Columns 'x86' and 'ARM' list the corresponding hardware instructions (following a `CMP` instruction).*
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### FPROUND
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The FPROUND instruction changes the rounding mode for all subsequent FPU operations depending on a two-bit flag. The flag is calculated by rotating A `imm8` bits to the right and taking the two least-significant bits:
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```
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rounding flag = (A >>> imm8)[1:0]
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```
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|rounding flag|rounding mode|
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|-------|------------|
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|00|roundTiesToEven|
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|01|roundTowardNegative|
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|10|roundTowardPositive|
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|11|roundTowardZero|
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The rounding modes are defined by the IEEE-754 standard.
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*The two-bit flag value exactly corresponds to bits 13-14 of the x86 `MXCSR` register and bits 23 and 22 (reversed) of the ARM `FPSCR` register.*
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### JUMP
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If the jump condition is `true`, the JUMP instruction performs a forward jump relative to the value of `pc`. The forward offset is equal to `16 * (imm8[6:0] + 1)` bytes (1-128 instructions forward).
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### CALL
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If the jump condition is `true`, the CALL instruction pushes the value of `pc` (program counter) onto the stack and then performs a forward jump relative to the value of `pc`. The forward offset is equal to `16 * (imm8[6:0] + 1)` bytes (1-128 instructions forward).
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### RET
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If the stack is not empty, the RET instruction pops the return address from the stack (it's the instruction following the previous CALL) and jumps to it.
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## Reference implementation
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A portable C++ implementation of all integer and floating point instructions is available in [instructionsPortable.cpp](../src/instructionsPortable.cpp).
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# RandomX instruction encoding
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The instruction set was designed in such way that any random 16-byte word is a valid instruction and any sequence of valid instructions is a valid program. There are no syntax rules.
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## RandomX instruction set
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RandomX uses a simple low-level language (instruction set), which was designed so that any random bitstring forms a valid program.
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The encoding of each 128-bit instruction word is following:
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Each RandomX instruction has a length of 128 bits. The encoding is following:
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## opcode
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There are 256 opcodes, which are distributed between 3 groups of instructions. There are 31 distinct operations (each operation can be encoded using multiple opcodes - for example opcodes `0x00` to `0x0d` correspond to integer addition).
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*All flags are aligned to an 8-bit boundary for easier decoding.*
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**Table 1: Instruction groups**
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|group|# operations|# opcodes||
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|---------|-----------------|----|-|
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|integer (IA)|22|144|56.3%|
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|floating point (FP)|5|76|29.7%|
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|control (CL)|4|36|14.0%
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||**31**|**256**|**100%**
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#### Opcode
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There are 256 opcodes, which are distributed between 30 instructions based on their weight (how often they will occur in the program on average). Instructions are divided into 5 groups:
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Full description of all instructions: [isa-ops.md](isa-ops.md).
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|group|number of opcodes||comment|
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|---------|-----------------|----|------|
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|IA|115|44.9%|integer arithmetic operations
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|IS|21|8.2%|bitwise shift and rotate
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|FA|70|27.4%|floating point arithmetic operations
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|FS|8|3.1%|floating point single-input operations
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|CF|42|16.4%|control flow instructions (branches)
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||**256**|**100%**
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## A.LOC
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**Table 2: `A.LOC` encoding**
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#### Operand A
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The first 64-bit operand is read from memory. The location is determined by the `loc(a)` flag:
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|bits|description|
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|----|--------|
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|0-1|`A.LOC.W` flag|
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|2-5|Reserved|
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|6-7|`A.LOC.X` flag|
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|loc(a)[2:0]|read A from|address size (W)
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The `A.LOC.W` flag determines the address width when reading operand A from the scratchpad:
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**Table 3: Operand A read address width**
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|`A.LOC.W`|address width (W)
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|---------|-|-|
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|000|dataset|32 bits|
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|001|dataset|32 bits|
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|010|dataset|32 bits|
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|011|dataset|32 bits|
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|100|scratchpad|15 bits|
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|101|scratchpad|11 bits|
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|110|scratchpad|11 bits|
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|111|scratchpad|11 bits|
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|0|15 bits (256 KiB)|
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|1-3|11 bits (16 KiB)|
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Flag `reg(a)` encodes an integer register `r0`-`r7`. The read address is calculated as:
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If the `A.LOC.W` flag is zero, the address space covers the whole 256 KiB scratchpad. Otherwise, just the first 16 KiB of the scratchpad are addressed.
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If the `A.LOC.X` flag is zero, the instruction mixes the scratchpad read address into the `mx` register using XOR. This mixing happens before the address is truncated to W bits (see pseudocode below).
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## A.REG
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**Table 4: `A.REG` encoding**
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|bits|description|
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|----|--------|
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|0-2|`A.REG.R` flag|
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|3-7|Reserved|
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The `A.REG.R` flag encodes "readAddressRegister", which is an integer register `r0`-`r7` to be used for scratchpad read address generation. Read address is generated as follows (pseudocode):
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```python
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readAddressRegister = IntegerRegister(A.REG.R)
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readAddressRegister = readAddressRegister XOR SignExtend(A.mask32)
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readAddress = readAddressRegister[31:0]
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# dataset is read if the ic register is divisible by 64
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IF ic mod 64 == 0:
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DatasetRead(readAddress)
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# optional mixing into the mx register
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IF A.LOC.X == 0:
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mx = mx XOR readAddress
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# truncate to W bits
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W = GetAddressWidth(A.LOC.W)
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readAddress = readAddress[W-1:0]
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```
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reg(a) = reg(a) XOR signExtend(addr(a))
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read_addr = reg(a)[W-1:0]
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Note that the value of the read address register is modified during address generation.
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## B.LOC
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**Table 5: `B.LOC` encoding**
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|bits|description|
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|----|--------|
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|0-1|`B.LOC.L` flag|
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|0-2|`B.LOC.C` flag|
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|3-7|Reserved|
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The `B.LOC.L` flag determines the B operand. It can be either a register or immediate value.
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**Table 6: Operand B**
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|`B.LOC.L`|IA/DIV|IA/SHIFT|IA/MATH|FP|CL|
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|----|--------|----|------|----|---|
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|0|register|register|register|register|register|
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|1|`imm32`|register|register|register|register|
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|2|`imm32`|`imm8`|register|register|register|
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|3|`imm32`|`imm8`|`imm32`|register|register|
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Integer instructions are split into 3 classes: integer division (IA/DIV), shift and rotate (IA/SHIFT) and other (IA/MATH). Floating point (FP) and control (CL) instructions always use a register operand.
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Register to be used as operand B is encoded in the `B.REG.R` flag (see below).
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The `B.LOC.C` flag determines the condition for the JUMP and CALL instructions. The flag partially overlaps with the `B.LOC.L` flag.
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## B.REG
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**Table 7: `B.REG` encoding**
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|bits|description|
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|----|--------|
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|0-2|`B.REG.R` flag|
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|3-7|Reserved|
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Register encoded by the `B.REG.R` depends on the instruction group:
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**Table 8: Register operands by group**
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|group|registers|
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|----|--------|
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|IA|`r0`-`r7`|
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|FP|`f0`-`f7`|
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|CL|`r0`-`r7`|
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## C.LOC
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**Table 9: `C.LOC` encoding**
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|bits|description|
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|----|--------|
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|0-1|`C.LOC.W` flag|
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|2|`C.LOC.R` flag|
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|3-6|Reserved|
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|7|`C.LOC.H` flag|
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The `C.LOC.W` flag determines the address width when writing operand C to the scratchpad:
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**Table 10: Operand C write address width**
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|`C.LOC.W`|address width (W)
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|---------|-|-|
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|0|15 bits (256 KiB)|
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|1-3|11 bits (16 KiB)|
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If the `C.LOC.W` flag is zero, the address space covers the whole 256 KiB scratchpad. Otherwise, just the first 16 KiB of the scratchpad are addressed.
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The `C.LOC.R` determines the destination where operand C is written:
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**Table 11: Operand C destination**
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|`C.LOC.R`|groups IA, CL|group FP
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|---------|-|-|
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|0|scratchpad|register
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|1|register|register + scratchpad
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Integer and control instructions (groups IA and CL) write either to the scratchpad or to a register. Floating point instructions always write to a register and can also write to the scratchpad. In that case, flag `C.LOC.H` determines if the low or high half of the register is written:
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**Table 12: Floating point register write**
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|`C.LOC.H`|write bits|
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|---------|----------|
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|0|0-63|
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|1|64-127|
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## C.REG
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**Table 13: `C.REG` encoding**
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|bits|description|
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|----|--------|
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|0-2|`C.REG.R` flag|
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|3-7|Reserved|
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The destination register encoded in the `C.REG.R` flag encodes both the write address register (if writing to the scratchpad) and the destination register (if writing to a register). The destination register depends on the instruction group (see Table 8). Write address is always generated from an integer register:
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```python
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writeAddressRegister = IntegerRegister(C.REG.R)
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writeAddress = writeAddressRegister[31:0] XOR C.mask32
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# truncate to W bits
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W = GetAddressWidth(C.LOC.W)
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writeAddress = writeAddress [W-1:0]
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```
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`W` is the address width from the above table. For reading from the scratchpad, `read_addr` is multiplied by 8 for 8-byte aligned access.
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#### Operand B
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The second operand is loaded either from a register or from an immediate value encoded within the instruction. The `reg(b)` flag encodes an integer register (instruction groups IA and IS) or a floating point register (instruction group FA). Instruction group FS doesn't use operand B.
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## imm8
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`imm8` is an 8-bit immediate value that is used as the B operand by IA/SHIFT instructions (see Table 6). Additionally, it's used by some control instructions.
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|loc(b)[2:0]|B (IA)|B (IS)|B (FA)|B (FS)
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|---------|-|-|-|-|
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|000|integer `reg(b)`|integer `reg(b)`|floating point `reg(b)`|-
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|001|integer `reg(b)`|integer `reg(b)`|floating point `reg(b)`|-
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|010|integer `reg(b)`|integer `reg(b)`|floating point `reg(b)`|-
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|011|integer `reg(b)`|integer `reg(b)`|floating point `reg(b)`|-
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|100|integer `reg(b)`|`imm8`|floating point `reg(b)`|-
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|101|integer `reg(b)`|`imm8`|floating point `reg(b)`|-
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|110|`imm32`|`imm8`|floating point `reg(b)`|-
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|111|`imm32`|`imm8`|floating point `reg(b)`|-
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## A.mask32
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`A.mask32` is a 32-bit address mask that is used to calculate the read address for the A operand. It's sign-extended to 64 bits before use.
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`imm8` is an 8-bit immediate value, which is used for shift and rotate integer instructions (group IS). Only bits 0-5 are used.
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## imm32
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`imm32` is a 32-bit immediate value which is used for integer instructions from groups IA/DIV and IA/OTHER (see Table 6). The immediate value is sign-extended for instructions that expect 64-bit operands.
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`imm32` is a 32-bit immediate value which is used for integer instructions from group IA.
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Floating point instructions don't use immediate values.
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#### Operand C
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The third operand is the location where the result is stored. It can be a register or a 64-bit scratchpad location, depending on the value of flag `loc(c)`.
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|loc\(c\)[2:0]|address size (W)| C (IA, IS)|C (FA, FS)
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|---------|-|-|-|-|-|
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|000|15 bits|scratchpad|floating point `reg(c)`
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|001|11 bits|scratchpad|floating point `reg(c)`
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|010|11 bits|scratchpad|floating point `reg(c)`
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|011|11 bits|scratchpad|floating point `reg(c)`
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|100|15 bits|integer `reg(c)`|floating point `reg(c)`, scratchpad
|
||||
|101|11 bits|integer `reg(c)`|floating point `reg(c)`, scratchpad
|
||||
|110|11 bits|integer `reg(c)`|floating point `reg(c)`, scratchpad
|
||||
|111|11 bits|integer `reg(c)`|floating point `reg(c)`, scratchpad
|
||||
|
||||
Integer operations write either to the scratchpad or to a register. Floating point operations always write to a register and can also write to the scratchpad. In that case, bit 3 of the `loc(c)` flag determines if the low or high half of the register is written:
|
||||
|
||||
|loc\(c\)[3]|write to scratchpad|
|
||||
|------------|-----------------------|
|
||||
|0|floating point `reg(c)[63:0]`
|
||||
|1|floating point `reg(c)[127:64]`
|
||||
|
||||
The FPROUND instruction is an exception and always writes the low half of the register.
|
||||
|
||||
For writing to the scratchpad, an integer register is always used to calculate the address:
|
||||
```
|
||||
write_addr = 8 * (addr(c) XOR reg(c)[31:0])[W-1:0]
|
||||
```
|
||||
*CPUs are typically designed for a 2:1 load:store ratio, so each VM instruction performs on average 1 memory read and 0.5 writes to memory.*
|
||||
|
||||
#### imm8
|
||||
An 8-bit immediate value that is used as the shift/rotate count by group IS instructions and as the jump offset of the CALL instruction.
|
||||
|
||||
#### addr(a)
|
||||
A 32-bit address mask that is used to calculate the read address for the A operand. It's sign-extended to 64 bits.
|
||||
|
||||
#### addr\(c\)
|
||||
A 32-bit address mask that is used to calculate the write address for the C operand. `addr(c)` is equal to `imm32`.
|
||||
|
||||
### ALU instructions
|
||||
|
||||
|weight|instruction|group|signed|A width|B width|C|C width|
|
||||
|-|-|-|-|-|-|-|-|
|
||||
|10|ADD_64|IA|no|64|64|`A + B`|64|
|
||||
|2|ADD_32|IA|no|32|32|`A + B`|32|
|
||||
|10|SUB_64|IA|no|64|64|`A - B`|64|
|
||||
|2|SUB_32|IA|no|32|32|`A - B`|32|
|
||||
|21|MUL_64|IA|no|64|64|`A * B`|64|
|
||||
|10|MULH_64|IA|no|64|64|`A * B`|64|
|
||||
|15|MUL_32|IA|no|32|32|`A * B`|64|
|
||||
|15|IMUL_32|IA|yes|32|32|`A * B`|64|
|
||||
|10|IMULH_64|IA|yes|64|64|`A * B`|64|
|
||||
|1|DIV_64|IA|no|64|32|`A / B`|32|
|
||||
|1|IDIV_64|IA|yes|64|32|`A / B`|32|
|
||||
|4|AND_64|IA|no|64|64|`A & B`|64|
|
||||
|2|AND_32|IA|no|32|32|`A & B`|32|
|
||||
|4|OR_64|IA|no|64|64|`A | B`|64|
|
||||
|2|OR_32|IA|no|32|32|`A | B`|32|
|
||||
|4|XOR_64|IA|no|64|64|`A ^ B`|64|
|
||||
|2|XOR_32|IA|no|32|32|`A ^ B`|32|
|
||||
|3|SHL_64|IS|no|64|6|`A << B`|64|
|
||||
|3|SHR_64|IS|no|64|6|`A >> B`|64|
|
||||
|3|SAR_64|IS|yes|64|6|`A >> B`|64|
|
||||
|6|ROL_64|IS|no|64|6|`A <<< B`|64|
|
||||
|6|ROR_64|IS|no|64|6|`A >>> B`|64|
|
||||
|
||||
##### 32-bit operations
|
||||
Instructions ADD_32, SUB_32, AND_32, OR_32, XOR_32 only use the low-order 32 bits of the input operands. The result of these operations is 32 bits long and bits 32-63 of C are set to zero.
|
||||
|
||||
##### Multiplication
|
||||
There are 5 different multiplication operations. MUL_64 and MULH_64 both take 64-bit unsigned operands, but MUL_64 produces the low 64 bits of the result and MULH_64 produces the high 64 bits. MUL_32 and IMUL_32 use only the low-order 32 bits of the operands and produce a 64-bit result. The signed variant interprets the arguments as signed integers. IMULH_64 takes two 64-bit signed operands and produces the high-order 64 bits of the result.
|
||||
|
||||
##### Division
|
||||
For the division instructions, the dividend is 64 bits long and the divisor 32 bits long. The IDIV_64 instruction interprets both operands as signed integers. In case of division by zero or signed overflow, the result is equal to the dividend `A`.
|
||||
|
||||
*Division by zero can be handled without branching by a conditional move. Signed overflow happens only for the signed variant when the minimum negative value is divided by -1. This rare case must be handled in x86 (ARM produces the "correct" result).*
|
||||
|
||||
##### Shift and rotate
|
||||
The shift/rotate instructions use just the bottom 6 bits of the `B` operand (`imm8` is used as the immediate value). All treat `A` as unsigned except SAR_64, which performs an arithmetic right shift by copying the sign bit.
|
||||
|
||||
### FPU instructions
|
||||
|
||||
|weight|instruction|group|C|
|
||||
|-|-|-|-|
|
||||
|20|FPADD|FA|`A + B`|
|
||||
|20|FPSUB|FA|`A - B`|
|
||||
|22|FPMUL|FA|`A * B`|
|
||||
|8|FPDIV|FA|`A / B`|
|
||||
|6|FPSQRT|FS|`sqrt(abs(A))`|
|
||||
|2|FPROUND|FS|`convertSigned52(A)`|
|
||||
|
||||
All floating point instructions apart FPROUND are vector instructions that operate on two packed double precision floating point values.
|
||||
|
||||
#### Conversion of operand A
|
||||
Operand A is loaded from memory as a 64-bit value. All floating point instructions apart FPROUND interpret A as two packed 32-bit signed integers and convert them into two packed double precision floating point values.
|
||||
|
||||
The FPROUND instruction has a scalar output and interprets A as a 64-bit signed integer. The 11 least-significant bits are cleared before conversion to a double precision format. This is done so the number fits exactly into the 52-bit mantissa without rounding. Output of FPROUND is always written into the lower half of the result register and only this lower half may be written into the scratchpad.
|
||||
|
||||
#### Rounding
|
||||
FPU instructions conform to the IEEE-754 specification, so they must give correctly rounded results. Initial rounding mode is *roundTiesToEven*. Rounding mode can be changed by the `FPROUND` instruction. Denormal values must be flushed to zero.
|
||||
|
||||
#### NaN
|
||||
If an operation produces NaN, the result is converted into positive zero. NaN results may never be written into registers or memory. Only division and multiplication must be checked for NaN results (`0.0 / 0.0` and `0.0 * Infinity` result in NaN).
|
||||
|
||||
##### FPROUND
|
||||
The FPROUND instruction changes the rounding mode for all subsequent FPU operations depending on the two least-significant bits of A.
|
||||
|
||||
|A[1:0]|rounding mode|
|
||||
|-------|------------|
|
||||
|00|roundTiesToEven|
|
||||
|01|roundTowardNegative|
|
||||
|10|roundTowardPositive|
|
||||
|11|roundTowardZero|
|
||||
|
||||
The rounding modes are defined by the IEEE-754 standard.
|
||||
|
||||
*The two-bit flag value exactly corresponds to bits 13-14 of the x86 `MXCSR` register and bits 23 and 22 (reversed) of the ARM `FPSCR` register.*
|
||||
|
||||
### Control instructions
|
||||
The following 2 control instructions are supported:
|
||||
|
||||
|weight|instruction|function|condition|
|
||||
|-|-|-|-|
|
||||
|20|CALL|near procedure call|(see condition table below)
|
||||
|22|RET|return from procedure|stack is not empty
|
||||
|
||||
Both instructions are conditional. If the condition evaluates to `false`, CALL and RET behave as "arithmetic no-op" and simply copy operand A into destination C without jumping.
|
||||
|
||||
##### CALL
|
||||
The CALL instruction uses a condition function, which takes the lower 32 bits of integer register `reg(b)` and the value `imm32` and evaluates a condition based on the `loc(b)` flag:
|
||||
|
||||
|loc(b)[2:0]|signed|jump condition|probability|*x86*|*ARM*
|
||||
|---|---|----------|-----|--|----|
|
||||
|000|no|`reg(b)[31:0] <= imm32`|0% - 100%|`JBE`|`BLS`
|
||||
|001|no|`reg(b)[31:0] > imm32`|0% - 100%|`JA`|`BHI`
|
||||
|010|yes|`reg(b)[31:0] - imm32 < 0`|50%|`JS`|`BMI`
|
||||
|011|yes|`reg(b)[31:0] - imm32 >= 0`|50%|`JNS`|`BPL`
|
||||
|100|yes|`reg(b)[31:0] - imm32` overflows|0% - 50%|`JO`|`BVS`
|
||||
|101|yes|`reg(b)[31:0] - imm32` doesn't overflow|50% - 100%|`JNO`|`BVC`
|
||||
|110|yes|`reg(b)[31:0] < imm32`|0% - 100%|`JL`|`BLT`
|
||||
|111|yes|`reg(b)[31:0] >= imm32`|0% - 100%|`JGE`|`BGE`
|
||||
|
||||
The 'signed' column specifies if the operands are interpreted as signed or unsigned 32-bit numbers. Column 'probability' lists the expected jump probability (range means that the actual value for a specific instruction depends on `imm32`). *Columns 'x86' and 'ARM' list the corresponding hardware instructions (following a `CMP` instruction).*
|
||||
|
||||
Taken CALL instruction pushes the values `A` and `pc` (program counter) onto the stack and then performs a forward jump relative to the value of `pc`. The forward offset is equal to `16 * (imm8[6:0] + 1)`. Maximum jump distance is therefore 128 instructions forward (this means that at least 4 correctly spaced CALL instructions are needed to form a loop in the program).
|
||||
|
||||
##### RET
|
||||
The RET instruction is taken only if the stack is not empty. Taken RET instruction pops the return address `raddr` from the stack (it's the instruction following the previous CALL), then pops a return value `retval` from the stack and sets `C = A XOR retval`. Finally, the instruction jumps back to `raddr`.
|
||||
|
||||
## Reference implementation
|
||||
A portable C++ implementation of all ALU and FPU instructions is available in [instructionsPortable.cpp](../src/instructionsPortable.cpp).
|
||||
## C.mask32
|
||||
`C.mask32` is a 32-bit address mask that is used to calculate the write address for the C operand. `C.mask32` is equal to `imm32`.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue