tevador
|
a7ffe8c19a
|
Mix dataset cacheline with registers r0-r7
|
2019-01-13 21:14:59 +01:00 |
|
tevador
|
48d85643de
|
Dataset intialization algorithm (AES)
|
2019-01-13 13:47:25 +01:00 |
|
tevador
|
67e741ff22
|
Reduced x86 code size by 512 bytes (and ecx -> and eax)
|
2019-01-12 20:27:35 +01:00 |
|
tevador
|
1426fcbab5
|
Print average program code size
Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
|
2019-01-12 16:05:09 +01:00 |
|
tevador
|
2756bcdcfe
|
Added magic division to JIT compiler
New B operand selection rules
|
2019-01-11 16:53:52 +01:00 |
|
tevador
|
451dfc5730
|
Optimized division by constants
|
2019-01-11 14:08:21 +01:00 |
|
tevador
|
c02ee4291d
|
FPROUND - variable flag offset
|
2019-01-11 10:52:12 +01:00 |
|
tevador
|
e487092f07
|
Simplified CALL and RET
|
2019-01-11 10:18:24 +01:00 |
|
tevador
|
557241cd95
|
JUMP instruction
|
2019-01-11 09:58:06 +01:00 |
|
tevador
|
6941b2cb69
|
Reworked instruction set documentation
|
2019-01-10 23:36:53 +01:00 |
|
tevador
|
d1a808643d
|
Random accesses - JIT compiler
|
2019-01-10 22:04:55 +01:00 |
|
tevador
|
b71e0eec65
|
Optimizations to reduce code size under 32K
|
2019-01-08 14:50:31 +01:00 |
|
tevador
|
b6d654291f
|
90 address transformations
|
2019-01-08 12:19:19 +01:00 |
|
tevador
|
2f6a599ff6
|
Inlined calls for memory read
|
2019-01-07 17:44:43 +01:00 |
|
tevador
|
6519fed4d1
|
Combined prefetch + read into a single step
|
2019-01-07 11:26:43 +01:00 |
|
tevador
|
4189e4ebc6
|
Original number of VM instructions
|
2019-01-06 17:23:05 +01:00 |
|
tevador
|
619bee5418
|
Random dataset accesses - asm only
Initial support for large pages
|
2019-01-04 19:44:15 +01:00 |
|
tevador
|
bf8397b08d
|
Updated specification
|
2018-12-31 19:27:31 +01:00 |
|
tevador
|
3caecc7646
|
Vector FPU instructions
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
|
2018-12-31 19:06:45 +01:00 |
|
tevador
|
a09bee8d60
|
js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up)
|
2018-12-28 14:18:41 +01:00 |
|
tevador
|
76b6b05cf2
|
Unconditional RET
|
2018-12-28 12:09:37 +01:00 |
|
tevador
|
39c569ae44
|
Fixed a potential crash in JitCompilerX86
|
2018-12-27 21:42:38 +01:00 |
|
tevador
|
5bc26348f1
|
Updated readme with performance data
Added --help option
|
2018-12-23 18:02:17 +01:00 |
|
tevador
|
03913d0e81
|
Run a single thread synchronously
|
2018-12-23 15:12:54 +01:00 |
|
tevador
|
c05947db09
|
Bug fixes
|
2018-12-23 14:25:22 +01:00 |
|
tevador
|
ca59925495
|
JitCompilerX86: use mmap to allocate an executable buffer
compile as c++11
|
2018-12-23 14:09:09 +01:00 |
|
tevador
|
740c40b218
|
8 branch conditions for CALL/RET
|
2018-12-21 22:41:35 +01:00 |
|
tevador
|
55afe9646f
|
Debuggable assembly generator
|
2018-12-21 21:09:55 +01:00 |
|
tevador
|
fce6e75689
|
Fixed copyright notice
|
2018-12-21 21:04:35 +01:00 |
|
tevador
|
ffa67295c4
|
Instruction statistics
|
2018-12-20 22:42:47 +01:00 |
|
tevador
|
1db7dd6e8b
|
Renamed immediate constants
|
2018-12-20 18:36:09 +01:00 |
|
tevador
|
b9d2d853aa
|
Support for multiple threads
|
2018-12-19 21:54:44 +01:00 |
|
tevador
|
cb12feaf91
|
t1ha2 hash for scratchpad digest
|
2018-12-19 12:38:10 +01:00 |
|
tevador
|
ed0bc906d6
|
JIT compiler for x86
|
2018-12-18 22:00:58 +01:00 |
|
tevador
|
ddc29cb4d3
|
Optimized x86 initialization
|
2018-12-16 15:10:03 +01:00 |
|
tevador
|
4f276541d2
|
Modified x86 register allocation
|
2018-12-16 13:43:18 +01:00 |
|
tevador
|
6332831ec1
|
Implemented cache shift
Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
|
2018-12-15 23:13:17 +01:00 |
|
tevador
|
4fc4b840f5
|
Updated documentation
|
2018-12-14 12:12:18 +01:00 |
|
tevador
|
d6ca408ce2
|
Merge branch 'master' of git@github.com:tevador/RandomX.git
|
2018-12-13 23:16:04 +01:00 |
|
tevador
|
cb0721056a
|
Assembly code generator for Windows 64-bit
|
2018-12-13 23:11:55 +01:00 |
tevador
|
52beccc309
|
Merge pull request #6 from vielmetti/patch-1
update ifdef for _rotr on aarch64
|
2018-12-12 16:46:39 +01:00 |
Edward Vielmetti
|
8ef8224270
|
update ifdef for _rotr on aarch64
Enables compilation on aarch64 (Packet c1.large.arm)
|
2018-12-12 07:54:33 -05:00 |
|
tevador
|
c9102ee88c
|
RandomX portable interpreter
|
2018-12-11 21:00:30 +01:00 |
|
tevador
|
072130c774
|
ALU/FPU test: Fixed MSVC x86 build
|
2018-11-20 22:41:34 +01:00 |
|
tevador
|
f19995d4c5
|
ALU and FPU tests
|
2018-11-19 22:53:19 +01:00 |
|
tevador
|
ec2d378fce
|
Updated specification
|
2018-11-18 11:38:33 +01:00 |
|
tevador
|
7e582c2815
|
Updated specification and instruction weights
|
2018-11-16 19:30:38 +01:00 |
|
tevador
|
1cc4fda4e7
|
Improved DRAM random access address space
|
2018-11-16 19:05:18 +01:00 |
|
tevador
|
d3739015ea
|
Fixed random read frequency
|
2018-11-16 18:12:32 +01:00 |
|
tevador
|
9ed71ae167
|
New DRAM reading pattern
New instruction weights
|
2018-11-16 16:35:17 +01:00 |