Commit Graph

307 Commits

Author SHA1 Message Date
tevador a145caa185 Fixed JIT compiler not producing the same code as genAsm and genNative 2019-02-15 16:43:52 +01:00
tevador f0d52fcf4d Fixed dependent constants 2019-02-15 11:38:20 +01:00
tevador ff0c5a58b3 More compact bytecode 2019-02-15 11:14:40 +01:00
tevador 447e8a1d4f Simplified division in interpreted mode
Fixed incorrect condition code in JitCompilerX86
Refactoring
2019-02-15 10:41:02 +01:00
tevador 1df975e583 Restored software AES support 2019-02-13 22:46:32 +01:00
tevador f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult 2019-02-13 00:01:34 +01:00
tevador 376c868ca0 Fixed wrong REX prefix in FDIV_M code 2019-02-12 23:20:10 +01:00
tevador 5a89c9b28e Use allocExecutableMemory 2019-02-12 18:18:02 +01:00
tevador 0b1761a846 Refactoring: mining/verification mode 2019-02-11 18:57:42 +01:00
tevador 69764966c0 Position independent loads fixed #21 2019-02-11 18:13:03 +01:00
tevador 49581e503a
Merge pull request #20 from antanst/fix-uname
Use portable uname flag, handle OpenBSD case of amd64
2019-02-11 16:00:17 +01:00
Antonis Anastasiadis dd2c894d69 Use portable uname flag, handle OpenBSD case of amd64 2019-02-11 16:51:34 +02:00
tevador e54697b952
Correct hashrate of i7-8550U with large pages 2019-02-10 00:20:21 +01:00
tevador 98c4ccf5ca Merge branch 'dev' 2019-02-09 20:02:14 +01:00
tevador 85b31342e1 Removed old documentation 2019-02-09 20:02:08 +01:00
tevador b8ce504be6 Added comments to hashAes1Rx4 and fillAes1Rx4
Fixed gcc compilation
Added performance numbers
2019-02-09 19:32:53 +01:00
tevador 2798d78717 Render imm32 as signed in RandomX code 2019-02-09 16:19:15 +01:00
tevador 9af0cbf108 Documentation formatting 2019-02-09 16:09:55 +01:00
tevador 32d827d0a6 Interpreter with bytecode
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
2019-02-09 15:45:26 +01:00
tevador a586751f6b Removed FPNEG instruction
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
2019-02-07 16:11:27 +01:00
tevador ac4462ad42 Renamed floating point instructions
Fixed negative source operand for FMUL_M and FDIV_M
2019-02-05 23:43:57 +01:00
tevador b417fd08ea 16 -> 8 chained programs
constant address loads are always from L3
2019-02-05 23:06:44 +01:00
tevador 1ee94bef2a Added ISWAP instruction
Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
2019-02-04 17:07:00 +01:00
tevador ab859879a2
loop body = 128 instructions 2019-01-27 20:10:03 +01:00
tevador 20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador 8f2abd6c05 NOP instruction
register load/store from L3
2019-01-27 18:19:49 +01:00
tevador 005c67f64c Added explicit STORE instructions
JIT compiler
2019-01-27 10:52:30 +01:00
tevador 7c049cce8d
Added store instructions 2019-01-24 21:49:39 +01:00
tevador 5b7df0c5e1
Test ASM for a new program structure 2019-01-24 19:35:11 +01:00
tevador d2cb086221 ASM code generator for "small" programs that fit into the uOP cache 2019-01-24 19:29:59 +01:00
tevador bd0dba88a8 4 scratchpad segments 2019-01-20 00:44:01 +01:00
tevador 16db607025 Scratchpad size increased to 1 MiB
New AES-based scratchpad hashing function
2019-01-18 23:51:18 +01:00
tevador 93c324709b Related to previous changes 2019-01-18 19:06:46 +01:00
tevador 89bc68d093 Memory-bound dataset initialization 2019-01-18 18:44:06 +01:00
tevador 4fb168e249 Large page support for cache
Bug fixes
2019-01-18 17:57:47 +01:00
tevador 8b1102ee05 Interpreter + async mode 2019-01-15 00:01:11 +01:00
tevador c2e0122e15
Comparison with CryptoNight 2019-01-13 23:51:12 +01:00
tevador a7ffe8c19a Mix dataset cacheline with registers r0-r7 2019-01-13 21:14:59 +01:00
tevador 48d85643de Dataset intialization algorithm (AES) 2019-01-13 13:47:25 +01:00
tevador 67e741ff22 Reduced x86 code size by 512 bytes (and ecx -> and eax) 2019-01-12 20:27:35 +01:00
tevador 1426fcbab5 Print average program code size
Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
2019-01-12 16:05:09 +01:00
tevador 2756bcdcfe Added magic division to JIT compiler
New B operand selection rules
2019-01-11 16:53:52 +01:00
tevador 451dfc5730 Optimized division by constants 2019-01-11 14:08:21 +01:00
tevador c02ee4291d FPROUND - variable flag offset 2019-01-11 10:52:12 +01:00
tevador e487092f07 Simplified CALL and RET 2019-01-11 10:18:24 +01:00
tevador 557241cd95 JUMP instruction 2019-01-11 09:58:06 +01:00
tevador 6941b2cb69 Reworked instruction set documentation 2019-01-10 23:36:53 +01:00
tevador d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador b71e0eec65 Optimizations to reduce code size under 32K 2019-01-08 14:50:31 +01:00
tevador b6d654291f 90 address transformations 2019-01-08 12:19:19 +01:00