tevador
f76e8c2e20
Reworked "FNEG" instruction to make ASIC optimizations more difficult
2019-02-13 00:01:34 +01:00
tevador
9af0cbf108
Documentation formatting
2019-02-09 16:09:55 +01:00
tevador
32d827d0a6
Interpreter with bytecode
...
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
2019-02-09 15:45:26 +01:00
tevador
2756bcdcfe
Added magic division to JIT compiler
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New B operand selection rules
2019-01-11 16:53:52 +01:00
tevador
c02ee4291d
FPROUND - variable flag offset
2019-01-11 10:52:12 +01:00
tevador
6941b2cb69
Reworked instruction set documentation
2019-01-10 23:36:53 +01:00
tevador
bf8397b08d
Updated specification
2018-12-31 19:27:31 +01:00
tevador
740c40b218
8 branch conditions for CALL/RET
2018-12-21 22:41:35 +01:00
tevador
1db7dd6e8b
Renamed immediate constants
2018-12-20 18:36:09 +01:00
tevador
6332831ec1
Implemented cache shift
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Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
2018-12-15 23:13:17 +01:00
tevador
4fc4b840f5
Updated documentation
2018-12-14 12:12:18 +01:00