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182 lines
5.9 KiB
Markdown
182 lines
5.9 KiB
Markdown
# RandomX instruction encoding
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The instruction set was designed in such way that any random 16-byte word is a valid instruction and any sequence of valid instructions is a valid program. There are no syntax rules.
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The encoding of each 128-bit instruction word is following:
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## opcode
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There are 256 opcodes, which are distributed between 3 groups of instructions. There are 31 distinct operations (each operation can be encoded using multiple opcodes - for example opcodes `0x00` to `0x0d` correspond to integer addition).
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**Table 1: Instruction groups**
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|group|# operations|# opcodes||
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|---------|-----------------|----|-|
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|integer (IA)|22|144|56.3%|
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|floating point (FP)|5|76|29.7%|
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|control (CL)|4|36|14.0%
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||**31**|**256**|**100%**
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Full description of all instructions: [isa-ops.md](isa-ops.md).
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## A.LOC
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**Table 2: `A.LOC` encoding**
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|bits|description|
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|----|--------|
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|0-1|`A.LOC.W` flag|
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|2-5|Reserved|
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|6-7|`A.LOC.X` flag|
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The `A.LOC.W` flag determines the address width when reading operand A from the scratchpad:
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**Table 3: Operand A read address width**
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|`A.LOC.W`|address width (W)|
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|---------|-|
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|0|15 bits (256 KiB)|
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|1-3|11 bits (16 KiB)|
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If the `A.LOC.W` flag is zero, the address space covers the whole 256 KiB scratchpad. Otherwise, just the first 16 KiB of the scratchpad are addressed.
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If the `A.LOC.X` flag is zero, the instruction mixes the scratchpad read address into the `mx` register using XOR. This mixing happens before the address is truncated to W bits (see pseudocode below).
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## A.REG
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**Table 4: `A.REG` encoding**
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|bits|description|
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|----|--------|
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|0-2|`A.REG.R` flag|
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|3-7|Reserved|
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The `A.REG.R` flag encodes "readAddressRegister", which is an integer register `r0`-`r7` to be used for scratchpad read address generation. Read address is generated as follows (pseudocode):
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```python
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readAddressRegister = IntegerRegister(A.REG.R)
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readAddressRegister = readAddressRegister XOR SignExtend(A.mask32)
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readAddress = readAddressRegister[31:0]
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# dataset is read if the ic register is divisible by 64
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IF ic mod 64 == 0:
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DatasetRead(readAddress)
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# optional mixing into the mx register
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IF A.LOC.X == 0:
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mx = mx XOR readAddress
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# truncate to W bits
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W = GetAddressWidth(A.LOC.W)
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readAddress = readAddress[W-1:0]
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```
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Note that the value of the read address register is modified during address generation.
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## B.LOC
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**Table 5: `B.LOC` encoding**
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|bits|description|
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|----|--------|
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|0-1|`B.LOC.L` flag|
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|0-2|`B.LOC.C` flag|
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|3-7|Reserved|
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The `B.LOC.L` flag determines the B operand. It can be either a register or immediate value.
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**Table 6: Operand B**
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|`B.LOC.L`|IA/DIV|IA/SHIFT|IA/MATH|FP|CL|
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|----|--------|----|------|----|---|
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|0|register|`imm8`|`imm32`|register|register|
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|1|`imm32`|register|register|register|register|
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|2|`imm32`|`imm8`|register|register|register|
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|3|`imm32`|register|register|register|register|
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Integer instructions are split into 3 classes: integer division (IA/DIV), shift and rotate (IA/SHIFT) and other (IA/MATH). Floating point (FP) and control (CL) instructions always use a register operand.
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Register to be used as operand B is encoded in the `B.REG.R` flag (see below).
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The `B.LOC.C` flag determines the condition for the JUMP and CALL instructions. The flag partially overlaps with the `B.LOC.L` flag.
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## B.REG
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**Table 7: `B.REG` encoding**
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|bits|description|
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|----|--------|
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|0-2|`B.REG.R` flag|
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|3-7|Reserved|
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Register encoded by the `B.REG.R` depends on the instruction group:
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**Table 8: Register operands by group**
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|group|registers|
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|----|--------|
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|IA|`r0`-`r7`|
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|FP|`f0`-`f7`|
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|CL|`r0`-`r7`|
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## C.LOC
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**Table 9: `C.LOC` encoding**
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|bits|description|
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|----|--------|
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|0-1|`C.LOC.W` flag|
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|2|`C.LOC.R` flag|
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|3-6|Reserved|
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|7|`C.LOC.H` flag|
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The `C.LOC.W` flag determines the address width when writing operand C to the scratchpad:
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**Table 10: Operand C write address width**
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|`C.LOC.W`|address width (W)|
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|---------|-|
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|0|15 bits (256 KiB)|
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|1-3|11 bits (16 KiB)|
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If the `C.LOC.W` flag is zero, the address space covers the whole 256 KiB scratchpad. Otherwise, just the first 16 KiB of the scratchpad are addressed.
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The `C.LOC.R` determines the destination where operand C is written:
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**Table 11: Operand C destination**
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|`C.LOC.R`|groups IA, CL|group FP
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|---------|-|-|
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|0|scratchpad|register
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|1|register|register + scratchpad
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Integer and control instructions (groups IA and CL) write either to the scratchpad or to a register. Floating point instructions always write to a register and can also write to the scratchpad. In that case, flag `C.LOC.H` determines if the low or high half of the register is written:
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**Table 12: Floating point register write**
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|`C.LOC.H`|write bits|
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|---------|----------|
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|0|0-63|
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|1|64-127|
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## C.REG
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**Table 13: `C.REG` encoding**
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|bits|description|
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|----|--------|
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|0-2|`C.REG.R` flag|
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|3-7|Reserved|
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The destination register encoded in the `C.REG.R` flag encodes both the write address register (if writing to the scratchpad) and the destination register (if writing to a register). The destination register depends on the instruction group (see Table 8). Write address is always generated from an integer register:
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```python
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writeAddressRegister = IntegerRegister(C.REG.R)
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writeAddress = writeAddressRegister[31:0] XOR C.mask32
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# truncate to W bits
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W = GetAddressWidth(C.LOC.W)
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writeAddress = writeAddress [W-1:0]
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```
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## imm8
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`imm8` is an 8-bit immediate value that is used as the B operand by IA/SHIFT instructions (see Table 6). Additionally, it's used by some control instructions.
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## A.mask32
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`A.mask32` is a 32-bit address mask that is used to calculate the read address for the A operand. It's sign-extended to 64 bits before use.
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## imm32
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`imm32` is a 32-bit immediate value which is used for integer instructions from groups IA/DIV and IA/OTHER (see Table 6). The immediate value is sign-extended for instructions that expect 64-bit operands.
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## C.mask32
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`C.mask32` is a 32-bit address mask that is used to calculate the write address for the C operand. `C.mask32` is equal to `imm32`.
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