104 lines
6.1 KiB
Markdown
104 lines
6.1 KiB
Markdown
# RandomX instruction listing
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## Integer instructions
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For integer instructions, the destination is always an integer register (register group R). Source operand (if applicable) can be either an integer register or memory value. If `dst` and `src` refer to the same register, most instructions use `imm32` as the source operand instead of the register. This is indicated in the 'src == dst' column.
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Memory operands are loaded as 8-byte values from the address indicated by `src`. This indirect addressing is marked with square brackets: `[src]`.
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|frequency|instruction|dst|src|`src == dst ?`|operation|
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|-|-|-|-|-|-|-|-|
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|12/256|IADD_R|R|R|`src = imm32`|`dst = dst + src`|
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|7/256|IADD_M|R|mem|`src = imm32`|`dst = dst + [src]`|
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|16/256|IADD_RC|R|R|`src = dst`|`dst = dst + src + imm32`|
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|12/256|ISUB_R|R|R|`src = imm32`|`dst = dst - src`|
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|7/256|ISUB_M|R|mem|`src = imm32`|`dst = dst - [src]`|
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|9/256|IMUL_9C|R|-|-|`dst = 9 * dst + imm32`|
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|16/256|IMUL_R|R|R|`src = imm32`|`dst = dst * src`|
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|4/256|IMUL_M|R|mem|`src = imm32`|`dst = dst * [src]`|
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|4/256|IMULH_R|R|R|`src = dst`|`dst = (dst * src) >> 64`|
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|1/256|IMULH_M|R|mem|`src = imm32`|`dst = (dst * [src]) >> 64`|
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|4/256|ISMULH_R|R|R|`src = dst`|`dst = (dst * src) >> 64` (signed)|
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|1/256|ISMULH_M|R|mem|`src = imm32`|`dst = (dst * [src]) >> 64` (signed)|
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|4/256|IDIV_C|R|-|-|`dst = dst + dst / imm32`|
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|4/256|ISDIV_C|R|-|-|`dst = dst + dst / imm32` (signed)|
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|2/256|INEG_R|R|-|-|`dst = -dst`|
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|16/256|IXOR_R|R|R|`src = imm32`|`dst = dst ^ src`|
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|4/256|IXOR_M|R|mem|`src = imm32`|`dst = dst ^ [src]`|
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|10/256|IROR_R|R|R|`src = imm32`|`dst = dst >>> src`|
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|4/256|ISWAP_R|R|R|`src = dst`|`temp = src; src = dst; dst = temp`|
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#### IMULH and ISMULH
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These instructions output the high 64 bits of the whole 128-bit multiplication result. The result differs for signed and unsigned multiplication (`IMULH` is unsigned, `ISMULH` is signed). The variants with a register source operand do not use `imm32` (they perform a squaring operation if `dst` equals `src`).
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#### IDIV_C and ISDIV_C
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The division instructions use a constant divisor, so they can be optimized into a [multiplication by fixed-point reciprocal](https://en.wikipedia.org/wiki/Division_algorithm#Division_by_a_constant). `IDIV_C` performs unsigned division (`imm32` is zero-extended to 64 bits), while `ISDIV_C` performs signed division. In the case of division by zero, the instructions become a no-op. In the very rare case of signed overflow, the destination register is set to zero.
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#### ISWAP_R
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This instruction swaps the values of two registers. If source and destination refer to the same register, the result is a no-op.
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## Floating point instructions
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For floating point instructions, the destination can be a group F or group E register. Source operand is either a group A register or a memory value.
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Memory operands are loaded as 8-byte values from the address indicated by `src`. The 8 byte value is interpreted as two 32-bit signed integers and implicitly converted to floating point format. The lower and upper memory operands are marked as `[src][0]` and `[src][1]`.
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|frequency|instruction|dst|src|operation|
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|-|-|-|-|-|-|-|
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|8/256|FSWAP_R|F+E|-|`(dst0, dst1) = (dst1, dst0)`|
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|20/256|FADD_R|F|A|`(dst0, dst1) = (dst0 + src0, dst1 + src1)`|
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|5/256|FADD_M|F|mem|`(dst0, dst1) = (dst0 + [src][0], dst1 + [src][1])`|
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|20/256|FSUB_R|F|A|`(dst0, dst1) = (dst0 - src0, dst1 - src1)`|
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|5/256|FSUB_M|F|mem|`(dst0, dst1) = (dst0 - [src][0], dst1 - [src][1])`|
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|6/256|FNEG_R|F|-|`(dst0, dst1) = (-dst0, -dst1)`|
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|20/256|FMUL_R|E|A|`(dst0, dst1) = (dst0 * src0, dst1 * src1)`|
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|4/256|FDIV_M|E|mem|`(dst0, dst1) = (dst0 / [src][0], dst1 / [src][1])`|
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|6/256|FSQRT_R|E|-|`(dst0, dst1) = (√dst0, √dst1)`|
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#### Denormal and NaN values
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Due to restrictions on the values of the floating point registers, no operation results in `NaN`.
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`FDIV_M` can produce a denormal result. In that case, the result is set to `DBL_MIN = 2.22507385850720138309e-308`, which is the smallest positive normal number.
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#### Rounding
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All floating point instructions give correctly rounded results. The rounding mode depends on the value of the `fprc` register:
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|`fprc`|rounding mode|
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|-------|------------|
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|0|roundTiesToEven|
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|1|roundTowardNegative|
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|2|roundTowardPositive|
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|3|roundTowardZero|
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The rounding modes are defined by the IEEE-754 standard.
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## Other instructions
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There are 4 special instructions that have more than one source operand or the destination operand is a memory value.
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|frequency|instruction|dst|src|operation|
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|-|-|-|-|-|
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|7/256|COND_R|R|R, `imm32`|`if(condition(src, imm32)) dst = dst + 1`
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|1/256|COND_M|R|mem, `imm32`|`if(condition([src], imm32)) dst = dst + 1`
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|1/256|CFROUND|`fprc`|R, `imm32`|`fprc = src >>> imm32`
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|16/256|ISTORE|mem|R|`[dst] = src`
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#### COND
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These instructions conditionally increment the destination register. The condition function depends on the `mod.cond` flag and takes the lower 32 bits of the source operand and the value `imm32`.
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|`mod.cond`|signed|`condition`|probability|*x86*|*ARM*
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|---|---|----------|-----|--|----|
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|0|no|`src <= imm32`|0% - 100%|`JBE`|`BLS`
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|1|no|`src > imm32`|0% - 100%|`JA`|`BHI`
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|2|yes|`src - imm32 < 0`|50%|`JS`|`BMI`
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|3|yes|`src - imm32 >= 0`|50%|`JNS`|`BPL`
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|4|yes|`src - imm32` overflows|0% - 50%|`JO`|`BVS`
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|5|yes|`src - imm32` doesn't overflow|50% - 100%|`JNO`|`BVC`
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|6|yes|`src < imm32`|0% - 100%|`JL`|`BLT`
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|7|yes|`src >= imm32`|0% - 100%|`JGE`|`BGE`
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The 'signed' column specifies if the operands are interpreted as signed or unsigned 32-bit numbers. Column 'probability' lists the expected probability the condition is true (range means that the actual value for a specific instruction depends on `imm32`). *Columns 'x86' and 'ARM' list the corresponding hardware instructions (following a `CMP` instruction).*
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#### CFROUND
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This instruction sets the value of the `fprc` register to the 2 least significant bits of the source register rotated right by `imm32`. This changes the rounding mode of all subsequent floating point instructions.
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#### ISTORE
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The `ISTORE` instruction stores the value of the source integer register to the memory at the address specified by the destination register. The `src` and `dst` register can be the same.
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