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134 commits 8 branches 5 tags 3.3 MiB
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88 commits

Author SHA1 Message Date
tevador
a1dc094c19 added epoch lag configuration 2019-03-11 23:43:52 +01:00
tevador
958d2bdc15 Fixed non-portable deserialization 2019-03-11 23:04:34 +01:00
tevador
2edf05cedc Implemented Dataset size increase per epoch 2019-03-10 23:14:03 +01:00
tevador
e65d9da66c Configurable parameters separated into configuration.h 2019-03-08 15:34:34 +01:00
tevador
096a7c0d7b Implemented virtual memory free 
Removed legacy AES code
 2019-03-08 11:46:03 +01:00
tevador
6e8c83fdb6 Fixed softAes compilation on PowerPC 2019-02-25 13:17:26 +01:00
tevador
7c012b4fee Fixed non-portable nonce serialization 
updated program.inc
 2019-02-25 09:31:35 +01:00
tevador
d9bc6cfeda Updated JIT compiler and assembly generator for new int -> float conversion 2019-02-24 17:24:06 +01:00
tevador
790b382eda Reworked conversion int -> float for register group E 2019-02-24 14:48:07 +01:00
tevador
f3b114af88 Replaced division instructions with IMUL_RCP 2019-02-22 17:48:26 +01:00
tevador
9d5f621d5c Removed divideByConstantCodegen 2019-02-22 13:47:47 +01:00
tevador
d9fcb34138 Fixed big endian load/store 2019-02-20 12:56:34 +01:00
tevador
88cf9d0728 Fixed 32-bit Windows build 2019-02-19 23:12:56 +01:00
tevador
219efce06c New command line options 2019-02-19 22:47:45 +01:00
tevador
f930d5d4dc Fixed a bug in FSWAP_R 2019-02-18 22:09:20 +01:00
tevador
c5309fae9e Fixed portable intrinsics compilation 2019-02-18 17:57:54 +01:00
tevador
bf34d27ecd Portable SSE2 intrinsics 2019-02-18 08:56:37 +01:00
tevador
954365634e Fixed alignment of VirtualMachine 2019-02-18 08:54:55 +01:00
tevador
dce8c74fa8 Fixed software AES in getResult 2019-02-18 08:45:39 +01:00
tevador
9a23bdb40d Fixed linux version of SquareHash 2019-02-18 08:44:28 +01:00
tevador
bfd557dac5 Added reference result 
Fixed undefined initial rounding mode
 2019-02-17 10:54:51 +01:00
tevador
923420f0a3 Fixed mining and verification mode not giving the same results 
Trace support in Assembly generator
 2019-02-16 23:18:45 +01:00
tevador
a145caa185 Fixed JIT compiler not producing the same code as genAsm and genNative 2019-02-15 16:43:52 +01:00
tevador
f0d52fcf4d Fixed dependent constants 2019-02-15 11:38:20 +01:00
tevador
ff0c5a58b3 More compact bytecode 2019-02-15 11:14:40 +01:00
tevador
447e8a1d4f Simplified division in interpreted mode 
Fixed incorrect condition code in JitCompilerX86
Refactoring
 2019-02-15 10:41:02 +01:00
tevador
1df975e583 Restored software AES support 2019-02-13 22:46:32 +01:00
tevador
f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult 2019-02-13 00:01:34 +01:00
tevador
376c868ca0 Fixed wrong REX prefix in FDIV_M code 2019-02-12 23:20:10 +01:00
tevador
5a89c9b28e Use allocExecutableMemory 2019-02-12 18:18:02 +01:00
tevador
0b1761a846 Refactoring: mining/verification mode 2019-02-11 18:57:42 +01:00
tevador
69764966c0 Position independent loads fixed #21 2019-02-11 18:13:03 +01:00
tevador
b8ce504be6 Added comments to hashAes1Rx4 and fillAes1Rx4 
Fixed gcc compilation
Added performance numbers
 2019-02-09 19:32:53 +01:00
tevador
2798d78717 Render imm32 as signed in RandomX code 2019-02-09 16:19:15 +01:00
tevador
32d827d0a6 Interpreter with bytecode 
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
 2019-02-09 15:45:26 +01:00
tevador
a586751f6b Removed FPNEG instruction 
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
 2019-02-07 16:11:27 +01:00
tevador
ac4462ad42 Renamed floating point instructions 
Fixed negative source operand for FMUL_M and FDIV_M
 2019-02-05 23:43:57 +01:00
tevador
b417fd08ea 16 -> 8 chained programs 
constant address loads are always from L3
 2019-02-05 23:06:44 +01:00
tevador
1ee94bef2a Added ISWAP instruction 
Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
 2019-02-04 17:07:00 +01:00
tevador
20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador
8f2abd6c05 NOP instruction 
register load/store from L3
 2019-01-27 18:19:49 +01:00
tevador
005c67f64c Added explicit STORE instructions 
JIT compiler
 2019-01-27 10:52:30 +01:00
tevador
d2cb086221 ASM code generator for "small" programs that fit into the uOP cache 2019-01-24 19:29:59 +01:00
tevador
bd0dba88a8 4 scratchpad segments 2019-01-20 00:44:01 +01:00
tevador
16db607025 Scratchpad size increased to 1 MiB 
New AES-based scratchpad hashing function
 2019-01-18 23:51:18 +01:00
tevador
93c324709b Related to previous changes 2019-01-18 19:06:46 +01:00
tevador
89bc68d093 Memory-bound dataset initialization 2019-01-18 18:44:06 +01:00
tevador
4fb168e249 Large page support for cache 
Bug fixes
 2019-01-18 17:57:47 +01:00
tevador
8b1102ee05 Interpreter + async mode 2019-01-15 00:01:11 +01:00
tevador
a7ffe8c19a Mix dataset cacheline with registers r0-r7 2019-01-13 21:14:59 +01:00