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175 commits 8 branches 5 tags 3.3 MiB
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34 commits

Author SHA1 Message Date
tevador
d49302561f Refactoring + comments 2019-04-12 13:32:22 +02:00
tevador
2e68c89740 Separate executeSuperscalar function 
Tweaked superscalar hash constants
 2019-04-11 18:31:13 +02:00
tevador
2132e5fef5 SuperscalarHash interpreter 
Linux assembly code
 2019-04-11 00:01:22 +02:00
tevador
b4c02051fa Reworked SuperscalarHash instruction set 
ASM and C code generator for SuperscalarHash
Support for Superscalar hash in the light mode
 2019-04-07 15:38:51 +02:00
tevador
77dbe14658 SuperscalarHash JIT compiler 
(unfinished)
 2019-04-06 12:00:56 +02:00
tevador
107270d93d Reduced Dataset size to 2 GiB with 8 memory accesses per block 
Disabled Dataset growth
 2019-03-22 12:53:16 +01:00
tevador
007f8599b9 Implemented branches in the interpreter 
Fixed x86 immediate encoding
 2019-03-20 23:38:37 +01:00
tevador
edde7672e0 initBlock: cycle columns, asm implementation 2019-03-15 18:00:51 +01:00
tevador
958d2bdc15 Fixed non-portable deserialization 2019-03-11 23:04:34 +01:00
tevador
2edf05cedc Implemented Dataset size increase per epoch 2019-03-10 23:14:03 +01:00
tevador
e65d9da66c Configurable parameters separated into configuration.h 2019-03-08 15:34:34 +01:00
tevador
096a7c0d7b Implemented virtual memory free 
Removed legacy AES code
 2019-03-08 11:46:03 +01:00
tevador
790b382eda Reworked conversion int -> float for register group E 2019-02-24 14:48:07 +01:00
tevador
f3b114af88 Replaced division instructions with IMUL_RCP 2019-02-22 17:48:26 +01:00
tevador
f930d5d4dc Fixed a bug in FSWAP_R 2019-02-18 22:09:20 +01:00
tevador
923420f0a3 Fixed mining and verification mode not giving the same results 
Trace support in Assembly generator
 2019-02-16 23:18:45 +01:00
tevador
447e8a1d4f Simplified division in interpreted mode 
Fixed incorrect condition code in JitCompilerX86
Refactoring
 2019-02-15 10:41:02 +01:00
tevador
f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult 2019-02-13 00:01:34 +01:00
tevador
b8ce504be6 Added comments to hashAes1Rx4 and fillAes1Rx4 
Fixed gcc compilation
Added performance numbers
 2019-02-09 19:32:53 +01:00
tevador
2798d78717 Render imm32 as signed in RandomX code 2019-02-09 16:19:15 +01:00
tevador
32d827d0a6 Interpreter with bytecode 
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
 2019-02-09 15:45:26 +01:00
tevador
1ee94bef2a Added ISWAP instruction 
Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
 2019-02-04 17:07:00 +01:00
tevador
d2cb086221 ASM code generator for "small" programs that fit into the uOP cache 2019-01-24 19:29:59 +01:00
tevador
bd0dba88a8 4 scratchpad segments 2019-01-20 00:44:01 +01:00
tevador
8b1102ee05 Interpreter + async mode 2019-01-15 00:01:11 +01:00
tevador
d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador
3caecc7646 Vector FPU instructions 
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
 2018-12-31 19:06:45 +01:00
tevador
76b6b05cf2 Unconditional RET 2018-12-28 12:09:37 +01:00
tevador
740c40b218 8 branch conditions for CALL/RET 2018-12-21 22:41:35 +01:00
tevador
ffa67295c4 Instruction statistics 2018-12-20 22:42:47 +01:00
tevador
1db7dd6e8b Renamed immediate constants 2018-12-20 18:36:09 +01:00
tevador
6332831ec1 Implemented cache shift 
Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
 2018-12-15 23:13:17 +01:00
tevador
cb0721056a Assembly code generator for Windows 64-bit 2018-12-13 23:11:55 +01:00
tevador
c9102ee88c RandomX portable interpreter 2018-12-11 21:00:30 +01:00