Commit graph

17 commits

Author SHA1 Message Date
tevador
682000b1a9 Unique scratchpad addresses - interpreter
Additional writes to L3
2019-04-16 18:58:44 +02:00
tevador
2132e5fef5 SuperscalarHash interpreter
Linux assembly code
2019-04-11 00:01:22 +02:00
tevador
77dbe14658 SuperscalarHash JIT compiler
(unfinished)
2019-04-06 12:00:56 +02:00
tevador
59bbb572c2 WIP 2019-03-28 15:27:10 +01:00
tevador
958d2bdc15 Fixed non-portable deserialization 2019-03-11 23:04:34 +01:00
tevador
f3b114af88 Replaced division instructions with IMUL_RCP 2019-02-22 17:48:26 +01:00
tevador
f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult 2019-02-13 00:01:34 +01:00
tevador
32d827d0a6 Interpreter with bytecode
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
2019-02-09 15:45:26 +01:00
tevador
a586751f6b Removed FPNEG instruction
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
2019-02-07 16:11:27 +01:00
tevador
ac4462ad42 Renamed floating point instructions
Fixed negative source operand for FMUL_M and FDIV_M
2019-02-05 23:43:57 +01:00
tevador
1ee94bef2a Added ISWAP instruction
Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
2019-02-04 17:07:00 +01:00
tevador
8f2abd6c05 NOP instruction
register load/store from L3
2019-01-27 18:19:49 +01:00
tevador
005c67f64c Added explicit STORE instructions
JIT compiler
2019-01-27 10:52:30 +01:00
tevador
d2cb086221 ASM code generator for "small" programs that fit into the uOP cache 2019-01-24 19:29:59 +01:00
tevador
1db7dd6e8b Renamed immediate constants 2018-12-20 18:36:09 +01:00
tevador
6332831ec1 Implemented cache shift
Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
2018-12-15 23:13:17 +01:00
tevador
cb0721056a Assembly code generator for Windows 64-bit 2018-12-13 23:11:55 +01:00