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172 commits 8 branches 5 tags 3.3 MiB
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26 commits

Author SHA1 Message Date
tevador
d9bc6cfeda Updated JIT compiler and assembly generator for new int -> float conversion 2019-02-24 17:24:06 +01:00
tevador
923420f0a3 Fixed mining and verification mode not giving the same results 
Trace support in Assembly generator
 2019-02-16 23:18:45 +01:00
tevador
a145caa185 Fixed JIT compiler not producing the same code as genAsm and genNative 2019-02-15 16:43:52 +01:00
tevador
32d827d0a6 Interpreter with bytecode 
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
 2019-02-09 15:45:26 +01:00
tevador
a586751f6b Removed FPNEG instruction 
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
 2019-02-07 16:11:27 +01:00
tevador
20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador
8f2abd6c05 NOP instruction 
register load/store from L3
 2019-01-27 18:19:49 +01:00
tevador
005c67f64c Added explicit STORE instructions 
JIT compiler
 2019-01-27 10:52:30 +01:00
tevador
d2cb086221 ASM code generator for "small" programs that fit into the uOP cache 2019-01-24 19:29:59 +01:00
tevador
4fb168e249 Large page support for cache 
Bug fixes
 2019-01-18 17:57:47 +01:00
tevador
a7ffe8c19a Mix dataset cacheline with registers r0-r7 2019-01-13 21:14:59 +01:00
tevador
67e741ff22 Reduced x86 code size by 512 bytes (and ecx -> and eax) 2019-01-12 20:27:35 +01:00
tevador
d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador
b71e0eec65 Optimizations to reduce code size under 32K 2019-01-08 14:50:31 +01:00
tevador
2f6a599ff6 Inlined calls for memory read 2019-01-07 17:44:43 +01:00
tevador
6519fed4d1 Combined prefetch + read into a single step 2019-01-07 11:26:43 +01:00
tevador
4189e4ebc6 Original number of VM instructions 2019-01-06 17:23:05 +01:00
tevador
619bee5418 Random dataset accesses - asm only 
Initial support for large pages
 2019-01-04 19:44:15 +01:00
tevador
3caecc7646 Vector FPU instructions 
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
 2018-12-31 19:06:45 +01:00
tevador
a09bee8d60 js -> jz to enable macro-op fusion on Intel CPUs (~1% speed-up) 2018-12-28 14:18:41 +01:00
tevador
55afe9646f Debuggable assembly generator 2018-12-21 21:09:55 +01:00
tevador
ed0bc906d6 JIT compiler for x86 2018-12-18 22:00:58 +01:00
tevador
ddc29cb4d3 Optimized x86 initialization 2018-12-16 15:10:03 +01:00
tevador
4f276541d2 Modified x86 register allocation 2018-12-16 13:43:18 +01:00
tevador
6332831ec1 Implemented cache shift 
Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
 2018-12-15 23:13:17 +01:00
tevador
cb0721056a Assembly code generator for Windows 64-bit 2018-12-13 23:11:55 +01:00