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245 commits 8 branches 5 tags 3.3 MiB
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31 commits

Author SHA1 Message Date
tevador
2b3a03a9dc Fixed FSCAL instruction causing group F registers to exceed their intended maximum value 2019-05-15 22:07:26 +02:00
tevador
c1314dc2a2 Use values from configuration.h in assembly code 2019-05-06 18:14:00 +02:00
tevador
a22e3b3cb0 30% faster JIT compiler 2019-05-04 19:40:25 +02:00
tevador
ca96270509 Group E exponent changed from a static value (-240) to dynamic 2019-04-30 21:14:50 +02:00
tevador
7f6bdd9a52 Code cleanup & refactoring 2019-04-28 16:42:45 +02:00
tevador
270a4f97fe Dataset size increased to 2080 MiB 
Implemented dataset base offset
Tweaked SuperscalarHash constants to prevent register collisions
 2019-04-26 16:05:30 +02:00
tevador
41b51a4858 Cleaned up legacy code 2019-04-21 14:07:32 +02:00
tevador
2e68c89740 Separate executeSuperscalar function 
Tweaked superscalar hash constants
 2019-04-11 18:31:13 +02:00
tevador
2132e5fef5 SuperscalarHash interpreter 
Linux assembly code
 2019-04-11 00:01:22 +02:00
tevador
6e3136b37f Fixed cache alignment 
Performance tuning
 2019-04-06 17:07:40 +02:00
tevador
77dbe14658 SuperscalarHash JIT compiler 
(unfinished)
 2019-04-06 12:00:56 +02:00
tevador
107270d93d Reduced Dataset size to 2 GiB with 8 memory accesses per block 
Disabled Dataset growth
 2019-03-22 12:53:16 +01:00
tevador
28ed776fbe Light JIT compiler - Linux 2019-03-22 11:00:21 +01:00
tevador
73a11f5c01 CompiledLightVirtualMachine 2019-03-21 20:44:59 +01:00
tevador
6b344b81fd initBlock asm version (disabled) 2019-03-17 00:57:48 +01:00
tevador
344f365c42 Updated constants according to the specs 2019-03-16 00:10:09 +01:00
tevador
d9bc6cfeda Updated JIT compiler and assembly generator for new int -> float conversion 2019-02-24 17:24:06 +01:00
tevador
f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult 2019-02-13 00:01:34 +01:00
tevador
69764966c0 Position independent loads fixed #21 2019-02-11 18:13:03 +01:00
tevador
32d827d0a6 Interpreter with bytecode 
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
 2019-02-09 15:45:26 +01:00
tevador
a586751f6b Removed FPNEG instruction 
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
 2019-02-07 16:11:27 +01:00
tevador
1ee94bef2a Added ISWAP instruction 
Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
 2019-02-04 17:07:00 +01:00
tevador
20eb549725 Merged load/store of integer and FP registers 2019-01-27 19:33:55 +01:00
tevador
8f2abd6c05 NOP instruction 
register load/store from L3
 2019-01-27 18:19:49 +01:00
tevador
005c67f64c Added explicit STORE instructions 
JIT compiler
 2019-01-27 10:52:30 +01:00
tevador
bd0dba88a8 4 scratchpad segments 2019-01-20 00:44:01 +01:00
tevador
a7ffe8c19a Mix dataset cacheline with registers r0-r7 2019-01-13 21:14:59 +01:00
tevador
67e741ff22 Reduced x86 code size by 512 bytes (and ecx -> and eax) 2019-01-12 20:27:35 +01:00
tevador
d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador
b6d654291f 90 address transformations 2019-01-08 12:19:19 +01:00
tevador
3caecc7646 Vector FPU instructions 
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
 2018-12-31 19:06:45 +01:00