sech1p/uwu
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Add uwu in Verilog

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sech1p 2021-08-28 00:13:57 +02:00
parent ba3f0acc56
commit 4a9a6c096e
Signed by: sech1p
GPG key ID: 44917CFA577DA652
2 changed files with 7 additions and 1 deletions
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README.md
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# uwu # uwu
uwu in every (soon™️) programming language in the world (75 languages and keeps growing) uwu in every (soon™️) programming language in the world (76 languages and keeps growing)
## Languages ## Languages
@ -61,6 +61,7 @@ uwu in every (soon™️) programming language in the world (75 languages and ke
- [Swift](uwu.swift) - [Swift](uwu.swift)
- [Tcl](uwu.tcl) - [Tcl](uwu.tcl)
- [Vala](uwu.vala) - [Vala](uwu.vala)
- [Verilog](uwu.v)
- [Vim script](uwu.vim) - [Vim script](uwu.vim)
- [Visual Basic .NET](uwu.vbnet) - [Visual Basic .NET](uwu.vbnet)
- [Xojo](uwu.xojo) - [Xojo](uwu.xojo)

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uwu.v Normal file
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module uwu;
initial begin
$display("uwu");
end
endmodule