Add uwu in Verilog

2021-08-28 00:13:57 +02:00 · 2021-08-28 00:13:57 +02:00 · 4a9a6c096e
parent ba3f0acc56
commit 4a9a6c096e
2 changed files with 7 additions and 1 deletions
--- a/README.md
+++ b/README.md
@ -1,6 +1,6 @@
 # uwu

-uwu in every (soon™️) programming language in the world (75 languages and keeps growing)
+uwu in every (soon™️) programming language in the world (76 languages and keeps growing)

 ## Languages

@ -61,6 +61,7 @@ uwu in every (soon™️) programming language in the world (75 languages and ke
 - [Swift](uwu.swift)
 - [Tcl](uwu.tcl)
 - [Vala](uwu.vala)
+- [Verilog](uwu.v)
 - [Vim script](uwu.vim)
 - [Visual Basic .NET](uwu.vbnet)
 - [Xojo](uwu.xojo)
--- a/uwu.v
+++ b/uwu.v
@ -0,0 +1,5 @@
+module uwu;
+  initial begin
+    $display("uwu");
+  end
+endmodule