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* Newer Intel and AMD CPUs have SSE extensions for SHA-1 and SHA-256 acceleration. * Add new cpu.c/cpu.h sources to detect the extensions, and use them in checksum.c if available. * Acceleration code is taken from https://github.com/noloader/SHA-Intrinsics.
124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
/*
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* Rufus: The Reliable USB Formatting Utility
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* CPU features detection
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* Copyright © 2022 Pete Batard <pete@akeo.ie>
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* Copyright © 2022 Jeffrey Walton <noloader@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#if (defined(CPU_X86_SHA1_ACCELERATION) || defined(CPU_X86_SHA256_ACCELERATION))
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#if defined(RUFUS_MSC_VERSION)
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#include <intrin.h>
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#elif (defined(RUFUS_GCC_VERSION) || defined(RUFUS_CLANG_VERSION))
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#include <x86Intrin.h>
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#elif defined(RUFUS_INTEL_VERSION)
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#include <immintrin.h>
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#endif
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#endif
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BOOL cpu_has_sha1_accel = FALSE;
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BOOL cpu_has_sha256_accel = FALSE;
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/*
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* Three elements must be in place to make a meaningful call to the
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* DetectSHA###Acceleration() calls. First, the compiler must support
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* the underlying intrinsics. Second, the platform must provide a
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* cpuid() function. And third, the cpu must actually support the SHA-1
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* and SHA-256 instructions.
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*
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* If any of the conditions are not met, then DetectSHA###Acceleration()
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* returns FALSE.
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*/
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/*
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* Detect if the processor supports SHA-1 acceleration. We only check for
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* the three ISAs we need - SSSE3, SSE4.1 and SHA. We don't check for OS
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* support or XSAVE because that's been enabled since Windows 2000.
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*/
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BOOL DetectSHA1Acceleration(void)
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{
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#if defined(CPU_X86_SHA1_ACCELERATION)
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#if defined(_MSC_VER)
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uint32_t regs0[4] = {0,0,0,0}, regs1[4] = {0,0,0,0}, regs7[4] = {0,0,0,0};
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const uint32_t SSSE3_BIT = 1u << 9; /* Function 1, Bit 9 of ECX */
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const uint32_t SSE41_BIT = 1u << 19; /* Function 1, Bit 19 of ECX */
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const uint32_t SHA_BIT = 1u << 29; /* Function 7, Bit 29 of EBX */
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__cpuid(regs0, 0);
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const uint32_t highest = regs0[0]; /*EAX*/
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if (highest >= 0x01) {
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__cpuidex(regs1, 1, 0);
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}
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if (highest >= 0x07) {
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__cpuidex(regs7, 7, 0);
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}
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return (regs1[2] /*ECX*/ & SSSE3_BIT) && (regs1[2] /*ECX*/ & SSE41_BIT) && (regs7[1] /*EBX*/ & SHA_BIT) ? TRUE : FALSE;
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#elif defined(__GNUC__) || defined(__clang__)
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/* __builtin_cpu_supports available in GCC 4.8.1 and above */
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return __builtin_cpu_supports("ssse3") && __builtin_cpu_supports("sse4.1") && __builtin_cpu_supports("sha") ? TRUE : FALSE;
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#elif defined(__INTEL_COMPILER)
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/* https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_may_i_use_cpu_feature */
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return _may_i_use_cpu_feature(_FEATURE_SSSE3|_FEATURE_SSE4_1|_FEATURE_SHA) ? TRUE : FALSE;
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#else
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return FALSE;
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#endif
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#else
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return FALSE;
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#endif
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}
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/*
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* Detect if the processor supports SHA-256 acceleration. We only check for
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* the three ISAs we need - SSSE3, SSE4.1 and SHA. We don't check for OS
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* support or XSAVE because that's been enabled since Windows 2000.
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*/
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BOOL DetectSHA256Acceleration(void)
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{
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#if defined(CPU_X86_SHA256_ACCELERATION)
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#if defined(_MSC_VER)
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uint32_t regs0[4] = {0,0,0,0}, regs1[4] = {0,0,0,0}, regs7[4] = {0,0,0,0};
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const uint32_t SSSE3_BIT = 1u << 9; /* Function 1, Bit 9 of ECX */
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const uint32_t SSE41_BIT = 1u << 19; /* Function 1, Bit 19 of ECX */
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const uint32_t SHA_BIT = 1u << 29; /* Function 7, Bit 29 of EBX */
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__cpuid(regs0, 0);
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const uint32_t highest = regs0[0]; /*EAX*/
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if (highest >= 0x01) {
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__cpuidex(regs1, 1, 0);
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}
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if (highest >= 0x07) {
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__cpuidex(regs7, 7, 0);
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}
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return (regs1[2] /*ECX*/ & SSSE3_BIT) && (regs1[2] /*ECX*/ & SSE41_BIT) && (regs7[1] /*EBX*/ & SHA_BIT) ? TRUE : FALSE;
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#elif defined(__GNUC__) || defined(__clang__)
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/* __builtin_cpu_supports available in GCC 4.8.1 and above */
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return __builtin_cpu_supports("ssse3") && __builtin_cpu_supports("sse4.1") && __builtin_cpu_supports("sha") ? TRUE : FALSE;
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#elif defined(__INTEL_COMPILER)
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/* https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_may_i_use_cpu_feature */
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return _may_i_use_cpu_feature(_FEATURE_SSSE3|_FEATURE_SSE4_1|_FEATURE_SHA) ? TRUE : FALSE;
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#else
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return FALSE;
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#endif
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#else
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return FALSE;
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#endif
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}
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