mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-08-15 00:23:14 +00:00
673 lines
No EOL
19 KiB
C++
673 lines
No EOL
19 KiB
C++
/*
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Copyright (c) 2018 tevador
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This file is part of RandomX.
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RandomX is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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RandomX is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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#include <iostream>
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#include <iomanip>
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#include <stdexcept>
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#include <sstream>
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#include <cmath>
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#include <cfloat>
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#include <climits>
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#include "vm_interpreted.hpp"
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#include "dataset.hpp"
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#include "intrin_portable.h"
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#include "reciprocal.h"
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namespace randomx {
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static int_reg_t Zero = 0;
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::setDataset(randomx_dataset* dataset) {
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datasetPtr = dataset;
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mem.memory = dataset->memory;
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::run(void* seed) {
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VmBase<Allocator, softAes>::generateProgram(seed);
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randomx_vm::initialize();
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execute();
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::executeBytecode(int_reg_t(&r)[RegistersCount], __m128d (&f)[RegisterCountFlt], __m128d (&e)[RegisterCountFlt], __m128d (&a)[RegisterCountFlt]) {
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for (int pc = 0; pc < RANDOMX_PROGRAM_SIZE; ++pc) {
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executeBytecode(pc, r, f, e, a);
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}
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}
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template<class Allocator, bool softAes>
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FORCE_INLINE void* InterpretedVm<Allocator, softAes>::getScratchpadAddress(InstructionByteCode& ibc) {
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uint32_t addr = (*ibc.isrc + ibc.imm) & ibc.memMask;
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return scratchpad + addr;
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}
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template<class Allocator, bool softAes>
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FORCE_INLINE __m128d InterpretedVm<Allocator, softAes>::maskRegisterExponentMantissa(__m128d x) {
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constexpr uint64_t mantissaMask64 = (1ULL << 52) - 1;
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const __m128d mantissaMask = _mm_castsi128_pd(_mm_set_epi64x(mantissaMask64, mantissaMask64));
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const __m128d exponentMask = _mm_load_pd((const double*)&config.eMask);
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x = _mm_and_pd(x, mantissaMask);
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x = _mm_or_pd(x, exponentMask);
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return x;
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::executeBytecode(int& pc, int_reg_t(&r)[RegistersCount], __m128d (&f)[RegisterCountFlt], __m128d (&e)[RegisterCountFlt], __m128d (&a)[RegisterCountFlt]) {
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auto& ibc = byteCode[pc];
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switch (ibc.type)
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{
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case InstructionType::IADD_RS: {
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*ibc.idst += (*ibc.isrc << ibc.shift) + ibc.imm;
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} break;
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case InstructionType::IADD_M: {
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*ibc.idst += load64(getScratchpadAddress(ibc));
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} break;
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case InstructionType::ISUB_R: {
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*ibc.idst -= *ibc.isrc;
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} break;
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case InstructionType::ISUB_M: {
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*ibc.idst -= load64(getScratchpadAddress(ibc));
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} break;
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case InstructionType::IMUL_R: { //also handles IMUL_RCP
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*ibc.idst *= *ibc.isrc;
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} break;
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case InstructionType::IMUL_M: {
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*ibc.idst *= load64(getScratchpadAddress(ibc));
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} break;
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case InstructionType::IMULH_R: {
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*ibc.idst = mulh(*ibc.idst, *ibc.isrc);
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} break;
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case InstructionType::IMULH_M: {
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*ibc.idst = mulh(*ibc.idst, load64(getScratchpadAddress(ibc)));
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} break;
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case InstructionType::ISMULH_R: {
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*ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(*ibc.isrc));
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} break;
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case InstructionType::ISMULH_M: {
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*ibc.idst = smulh(unsigned64ToSigned2sCompl(*ibc.idst), unsigned64ToSigned2sCompl(load64(getScratchpadAddress(ibc))));
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} break;
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case InstructionType::INEG_R: {
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*ibc.idst = ~(*ibc.idst) + 1; //two's complement negative
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} break;
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case InstructionType::IXOR_R: {
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*ibc.idst ^= *ibc.isrc;
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} break;
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case InstructionType::IXOR_M: {
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*ibc.idst ^= load64(getScratchpadAddress(ibc));
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} break;
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case InstructionType::IROR_R: {
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*ibc.idst = rotr(*ibc.idst, *ibc.isrc & 63);
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} break;
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case InstructionType::IROL_R: {
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*ibc.idst = rotl(*ibc.idst, *ibc.isrc & 63);
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} break;
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case InstructionType::ISWAP_R: {
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int_reg_t temp = *ibc.isrc;
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*ibc.isrc = *ibc.idst;
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*ibc.idst = temp;
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} break;
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case InstructionType::FSWAP_R: {
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*ibc.fdst = _mm_shuffle_pd(*ibc.fdst, *ibc.fdst, 1);
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} break;
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case InstructionType::FADD_R: {
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*ibc.fdst = _mm_add_pd(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FADD_M: {
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__m128d fsrc = load_cvt_i32x2(getScratchpadAddress(ibc));
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*ibc.fdst = _mm_add_pd(*ibc.fdst, fsrc);
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} break;
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case InstructionType::FSUB_R: {
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*ibc.fdst = _mm_sub_pd(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FSUB_M: {
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__m128d fsrc = load_cvt_i32x2(getScratchpadAddress(ibc));
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*ibc.fdst = _mm_sub_pd(*ibc.fdst, fsrc);
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} break;
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case InstructionType::FSCAL_R: {
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const __m128d mask = _mm_castsi128_pd(_mm_set1_epi64x(0x81F0000000000000));
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*ibc.fdst = _mm_xor_pd(*ibc.fdst, mask);
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} break;
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case InstructionType::FMUL_R: {
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*ibc.fdst = _mm_mul_pd(*ibc.fdst, *ibc.fsrc);
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} break;
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case InstructionType::FDIV_M: {
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__m128d fsrc = maskRegisterExponentMantissa(load_cvt_i32x2(getScratchpadAddress(ibc)));
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*ibc.fdst = _mm_div_pd(*ibc.fdst, fsrc);
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} break;
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case InstructionType::FSQRT_R: {
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*ibc.fdst = _mm_sqrt_pd(*ibc.fdst);
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} break;
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case InstructionType::CBRANCH: {
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*ibc.isrc += ibc.imm;
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if ((*ibc.isrc & ibc.memMask) == 0) {
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pc = ibc.target;
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}
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} break;
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case InstructionType::CFROUND: {
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setRoundMode(rotr(*ibc.isrc, ibc.imm) % 4);
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} break;
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case InstructionType::ISTORE: {
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store64(scratchpad + ((*ibc.idst + ibc.imm) & ibc.memMask), *ibc.isrc);
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} break;
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case InstructionType::NOP: {
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//nothing
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} break;
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default:
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UNREACHABLE;
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}
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::execute() {
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int_reg_t r[RegistersCount] = { 0 };
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__m128d f[RegisterCountFlt];
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__m128d e[RegisterCountFlt];
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__m128d a[RegisterCountFlt];
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for(unsigned i = 0; i < RegisterCountFlt; ++i)
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a[i] = _mm_load_pd(®.a[i].lo);
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precompileProgram(r, f, e, a);
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uint32_t spAddr0 = mem.mx;
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uint32_t spAddr1 = mem.ma;
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for(unsigned ic = 0; ic < RANDOMX_PROGRAM_ITERATIONS; ++ic) {
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uint64_t spMix = r[config.readReg0] ^ r[config.readReg1];
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spAddr0 ^= spMix;
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spAddr0 &= ScratchpadL3Mask64;
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spAddr1 ^= spMix >> 32;
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spAddr1 &= ScratchpadL3Mask64;
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for (unsigned i = 0; i < RegistersCount; ++i)
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r[i] ^= load64(scratchpad + spAddr0 + 8 * i);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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f[i] = load_cvt_i32x2(scratchpad + spAddr1 + 8 * i);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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e[i] = maskRegisterExponentMantissa(load_cvt_i32x2(scratchpad + spAddr1 + 8 * (RegisterCountFlt + i)));
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executeBytecode(r, f, e, a);
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mem.mx ^= r[config.readReg2] ^ r[config.readReg3];
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mem.mx &= CacheLineAlignMask;
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datasetRead(datasetOffset + mem.ma, r);
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std::swap(mem.mx, mem.ma);
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for (unsigned i = 0; i < RegistersCount; ++i)
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store64(scratchpad + spAddr1 + 8 * i, r[i]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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f[i] = _mm_xor_pd(f[i], e[i]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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_mm_store_pd((double*)(scratchpad + spAddr0 + 16 * i), f[i]);
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spAddr0 = 0;
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spAddr1 = 0;
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}
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for (unsigned i = 0; i < RegistersCount; ++i)
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store64(®.r[i], r[i]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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_mm_store_pd(®.f[i].lo, f[i]);
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for (unsigned i = 0; i < RegisterCountFlt; ++i)
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_mm_store_pd(®.e[i].lo, e[i]);
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}
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static int getConditionRegister(int(®isterUsage)[RegistersCount]) {
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int min = INT_MAX;
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int minIndex;
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for (unsigned i = 0; i < RegistersCount; ++i) {
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if (registerUsage[i] < min) {
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min = registerUsage[i];
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minIndex = i;
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}
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}
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return minIndex;
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}
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::datasetRead(uint32_t address, int_reg_t(&r)[RegistersCount]) {
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uint64_t* datasetLine = (uint64_t*)(mem.memory + address);
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for (int i = 0; i < RegistersCount; ++i)
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r[i] ^= datasetLine[i];
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}
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#include "instruction_weights.hpp"
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template<class Allocator, bool softAes>
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void InterpretedVm<Allocator, softAes>::precompileProgram(int_reg_t(&r)[RegistersCount], __m128d (&f)[RegisterCountFlt], __m128d (&e)[RegisterCountFlt], __m128d (&a)[RegisterCountFlt]) {
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int registerUsage[RegistersCount];
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for (unsigned i = 0; i < RegistersCount; ++i) {
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registerUsage[i] = -1;
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}
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for (unsigned i = 0; i < RANDOMX_PROGRAM_SIZE; ++i) {
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auto& instr = program(i);
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auto& ibc = byteCode[i];
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switch (instr.opcode) {
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CASE_REP(IADD_RS) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IADD_RS;
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ibc.idst = &r[dst];
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if (dst != RegisterNeedsDisplacement) {
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ibc.isrc = &r[src];
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ibc.shift = instr.getModShift();
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ibc.imm = 0;
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}
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else {
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ibc.isrc = &r[src];
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ibc.shift = instr.getModShift();
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ibc.imm = signExtend2sCompl(instr.getImm32());
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IADD_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IADD_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(ISUB_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::ISUB_R;
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ibc.idst = &r[dst];
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if (src != dst) {
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ibc.isrc = &r[src];
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}
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else {
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ibc.imm = signExtend2sCompl(instr.getImm32());
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ibc.isrc = &ibc.imm;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(ISUB_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::ISUB_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMUL_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IMUL_R;
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ibc.idst = &r[dst];
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if (src != dst) {
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ibc.isrc = &r[src];
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}
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else {
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ibc.imm = signExtend2sCompl(instr.getImm32());
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ibc.isrc = &ibc.imm;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMUL_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IMUL_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMULH_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IMULH_R;
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ibc.idst = &r[dst];
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ibc.isrc = &r[src];
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMULH_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::IMULH_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(ISMULH_R) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::ISMULH_R;
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ibc.idst = &r[dst];
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ibc.isrc = &r[src];
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registerUsage[dst] = i;
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} break;
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CASE_REP(ISMULH_M) {
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auto dst = instr.dst % RegistersCount;
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auto src = instr.src % RegistersCount;
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ibc.type = InstructionType::ISMULH_M;
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ibc.idst = &r[dst];
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ibc.imm = signExtend2sCompl(instr.getImm32());
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if (src != dst) {
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ibc.isrc = &r[src];
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ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
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}
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else {
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ibc.isrc = &Zero;
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ibc.memMask = ScratchpadL3Mask;
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}
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registerUsage[dst] = i;
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} break;
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CASE_REP(IMUL_RCP) {
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uint32_t divisor = instr.getImm32();
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if (divisor != 0) {
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auto dst = instr.dst % RegistersCount;
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ibc.type = InstructionType::IMUL_R;
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ibc.idst = &r[dst];
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ibc.imm = randomx_reciprocal(divisor);
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ibc.isrc = &ibc.imm;
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registerUsage[dst] = i;
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}
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else {
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ibc.type = InstructionType::NOP;
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}
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} break;
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CASE_REP(INEG_R) {
|
|
auto dst = instr.dst % RegistersCount;
|
|
ibc.type = InstructionType::INEG_R;
|
|
ibc.idst = &r[dst];
|
|
registerUsage[dst] = i;
|
|
} break;
|
|
|
|
CASE_REP(IXOR_R) {
|
|
auto dst = instr.dst % RegistersCount;
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.type = InstructionType::IXOR_R;
|
|
ibc.idst = &r[dst];
|
|
if (src != dst) {
|
|
ibc.isrc = &r[src];
|
|
}
|
|
else {
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
ibc.isrc = &ibc.imm;
|
|
}
|
|
registerUsage[dst] = i;
|
|
} break;
|
|
|
|
CASE_REP(IXOR_M) {
|
|
auto dst = instr.dst % RegistersCount;
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.type = InstructionType::IXOR_M;
|
|
ibc.idst = &r[dst];
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
if (src != dst) {
|
|
ibc.isrc = &r[src];
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
}
|
|
else {
|
|
ibc.isrc = &Zero;
|
|
ibc.memMask = ScratchpadL3Mask;
|
|
}
|
|
registerUsage[dst] = i;
|
|
} break;
|
|
|
|
CASE_REP(IROR_R) {
|
|
auto dst = instr.dst % RegistersCount;
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.type = InstructionType::IROR_R;
|
|
ibc.idst = &r[dst];
|
|
if (src != dst) {
|
|
ibc.isrc = &r[src];
|
|
}
|
|
else {
|
|
ibc.imm = instr.getImm32();
|
|
ibc.isrc = &ibc.imm;
|
|
}
|
|
registerUsage[dst] = i;
|
|
} break;
|
|
|
|
CASE_REP(IROL_R) {
|
|
auto dst = instr.dst % RegistersCount;
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.type = InstructionType::IROL_R;
|
|
ibc.idst = &r[dst];
|
|
if (src != dst) {
|
|
ibc.isrc = &r[src];
|
|
}
|
|
else {
|
|
ibc.imm = instr.getImm32();
|
|
ibc.isrc = &ibc.imm;
|
|
}
|
|
registerUsage[dst] = i;
|
|
} break;
|
|
|
|
CASE_REP(ISWAP_R) {
|
|
auto dst = instr.dst % RegistersCount;
|
|
auto src = instr.src % RegistersCount;
|
|
if (src != dst) {
|
|
ibc.idst = &r[dst];
|
|
ibc.isrc = &r[src];
|
|
ibc.type = InstructionType::ISWAP_R;
|
|
registerUsage[dst] = i;
|
|
registerUsage[src] = i;
|
|
}
|
|
else {
|
|
ibc.type = InstructionType::NOP;
|
|
}
|
|
} break;
|
|
|
|
CASE_REP(FSWAP_R) {
|
|
auto dst = instr.dst % RegistersCount;
|
|
ibc.type = InstructionType::FSWAP_R;
|
|
if (dst < RegisterCountFlt)
|
|
ibc.fdst = &f[dst];
|
|
else
|
|
ibc.fdst = &e[dst - RegisterCountFlt];
|
|
} break;
|
|
|
|
CASE_REP(FADD_R) {
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
auto src = instr.src % RegisterCountFlt;
|
|
ibc.type = InstructionType::FADD_R;
|
|
ibc.fdst = &f[dst];
|
|
ibc.fsrc = &a[src];
|
|
} break;
|
|
|
|
CASE_REP(FADD_M) {
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.type = InstructionType::FADD_M;
|
|
ibc.fdst = &f[dst];
|
|
ibc.isrc = &r[src];
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
} break;
|
|
|
|
CASE_REP(FSUB_R) {
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
auto src = instr.src % RegisterCountFlt;
|
|
ibc.type = InstructionType::FSUB_R;
|
|
ibc.fdst = &f[dst];
|
|
ibc.fsrc = &a[src];
|
|
} break;
|
|
|
|
CASE_REP(FSUB_M) {
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.type = InstructionType::FSUB_M;
|
|
ibc.fdst = &f[dst];
|
|
ibc.isrc = &r[src];
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
} break;
|
|
|
|
CASE_REP(FSCAL_R) {
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
ibc.fdst = &f[dst];
|
|
ibc.type = InstructionType::FSCAL_R;
|
|
} break;
|
|
|
|
CASE_REP(FMUL_R) {
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
auto src = instr.src % RegisterCountFlt;
|
|
ibc.type = InstructionType::FMUL_R;
|
|
ibc.fdst = &e[dst];
|
|
ibc.fsrc = &a[src];
|
|
} break;
|
|
|
|
CASE_REP(FDIV_M) {
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.type = InstructionType::FDIV_M;
|
|
ibc.fdst = &e[dst];
|
|
ibc.isrc = &r[src];
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
} break;
|
|
|
|
CASE_REP(FSQRT_R) {
|
|
auto dst = instr.dst % RegisterCountFlt;
|
|
ibc.type = InstructionType::FSQRT_R;
|
|
ibc.fdst = &e[dst];
|
|
} break;
|
|
|
|
CASE_REP(CBRANCH) {
|
|
ibc.type = InstructionType::CBRANCH;
|
|
//jump condition
|
|
int reg = getConditionRegister(registerUsage);
|
|
ibc.isrc = &r[reg];
|
|
ibc.target = registerUsage[reg];
|
|
int shift = instr.getModCond();
|
|
const uint64_t conditionMask = ConditionMask << instr.getModCond();
|
|
ibc.imm = signExtend2sCompl(instr.getImm32()) | (1ULL << shift);
|
|
ibc.memMask = ConditionMask << shift;
|
|
for (unsigned j = 0; j < RegistersCount; ++j) { //mark all registers as used
|
|
registerUsage[j] = i;
|
|
}
|
|
} break;
|
|
|
|
CASE_REP(CFROUND) {
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.isrc = &r[src];
|
|
ibc.type = InstructionType::CFROUND;
|
|
ibc.imm = instr.getImm32() & 63;
|
|
} break;
|
|
|
|
CASE_REP(ISTORE) {
|
|
auto dst = instr.dst % RegistersCount;
|
|
auto src = instr.src % RegistersCount;
|
|
ibc.type = InstructionType::ISTORE;
|
|
ibc.idst = &r[dst];
|
|
ibc.isrc = &r[src];
|
|
ibc.imm = signExtend2sCompl(instr.getImm32());
|
|
if (instr.getModCond() < StoreL3Condition)
|
|
ibc.memMask = (instr.getModMem() ? ScratchpadL1Mask : ScratchpadL2Mask);
|
|
else
|
|
ibc.memMask = ScratchpadL3Mask;
|
|
} break;
|
|
|
|
CASE_REP(NOP) {
|
|
ibc.type = InstructionType::NOP;
|
|
} break;
|
|
|
|
default:
|
|
UNREACHABLE;
|
|
}
|
|
}
|
|
}
|
|
|
|
template class InterpretedVm<AlignedAllocator<CacheLineSize>, false>;
|
|
template class InterpretedVm<AlignedAllocator<CacheLineSize>, true>;
|
|
template class InterpretedVm<LargePageAllocator, false>;
|
|
template class InterpretedVm<LargePageAllocator, true>;
|
|
} |