mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-08-15 00:23:14 +00:00
363 lines
No EOL
8.5 KiB
C++
363 lines
No EOL
8.5 KiB
C++
/*
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Copyright (c) 2018 tevador
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This file is part of RandomX.
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RandomX is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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RandomX is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with RandomX. If not, see<http://www.gnu.org/licenses/>.
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*/
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#include "instruction.hpp"
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#include "common.hpp"
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namespace randomx {
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void Instruction::print(std::ostream& os) const {
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os << names[opcode] << " ";
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auto handler = engine[opcode];
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(this->*handler)(os);
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}
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void Instruction::genAddressReg(std::ostream& os) const {
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os << (getModMem() ? "L1" : "L2") << "[r" << (int)src << std::showpos << (int32_t)getImm32() << std::noshowpos << "]";
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}
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void Instruction::genAddressRegDst(std::ostream& os) const {
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if (getModCond() < StoreL3Condition)
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os << (getModMem() ? "L1" : "L2");
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else
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os << "L3";
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os << "[r" << (int)dst << std::showpos << (int32_t)getImm32() << std::noshowpos << "]";
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}
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void Instruction::genAddressImm(std::ostream& os) const {
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os << "L3" << "[" << (getImm32() & ScratchpadL3Mask) << "]";
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}
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void Instruction::h_IADD_RS(std::ostream& os) const {
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os << "r" << (int)dst << ", r" << (int)src;
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if(dst == RegisterNeedsDisplacement) {
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os << ", " << (int32_t)getImm32();
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}
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os << ", SHFT " << (int)getModShift() << std::endl;
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}
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void Instruction::h_IADD_M(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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else {
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os << "r" << (int)dst << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_ISUB_R(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << (int32_t)getImm32() << std::endl;
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}
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}
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void Instruction::h_ISUB_M(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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else {
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os << "r" << (int)dst << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_IMUL_R(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << (int32_t)getImm32() << std::endl;
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}
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}
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void Instruction::h_IMUL_M(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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else {
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os << "r" << (int)dst << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_IMULH_R(std::ostream& os) const {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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void Instruction::h_IMULH_M(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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else {
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os << "r" << (int)dst << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_ISMULH_R(std::ostream& os) const {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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void Instruction::h_ISMULH_M(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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else {
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os << "r" << (int)dst << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_INEG_R(std::ostream& os) const {
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os << "r" << (int)dst << std::endl;
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}
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void Instruction::h_IXOR_R(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << (int32_t)getImm32() << std::endl;
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}
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}
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void Instruction::h_IXOR_M(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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else {
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os << "r" << (int)dst << ", ";
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genAddressImm(os);
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os << std::endl;
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}
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}
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void Instruction::h_IROR_R(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << (getImm32() & 63) << std::endl;
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}
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}
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void Instruction::h_IROL_R(std::ostream& os) const {
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if (src != dst) {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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else {
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os << "r" << (int)dst << ", " << (getImm32() & 63) << std::endl;
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}
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}
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void Instruction::h_IMUL_RCP(std::ostream& os) const {
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os << "r" << (int)dst << ", " << getImm32() << std::endl;
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}
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void Instruction::h_ISWAP_R(std::ostream& os) const {
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os << "r" << (int)dst << ", r" << (int)src << std::endl;
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}
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void Instruction::h_FSWAP_R(std::ostream& os) const {
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const char reg = (dst >= RegisterCountFlt) ? 'e' : 'f';
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auto dstIndex = dst % RegisterCountFlt;
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os << reg << dstIndex << std::endl;
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}
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void Instruction::h_FADD_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegisterCountFlt;
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os << "f" << dstIndex << ", a" << srcIndex << std::endl;
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}
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void Instruction::h_FADD_M(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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os << "f" << dstIndex << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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void Instruction::h_FSUB_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegisterCountFlt;
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os << "f" << dstIndex << ", a" << srcIndex << std::endl;
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}
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void Instruction::h_FSUB_M(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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os << "f" << dstIndex << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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void Instruction::h_FSCAL_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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os << "f" << dstIndex << std::endl;
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}
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void Instruction::h_FMUL_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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auto srcIndex = src % RegisterCountFlt;
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os << "e" << dstIndex << ", a" << srcIndex << std::endl;
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}
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void Instruction::h_FDIV_M(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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os << "e" << dstIndex << ", ";
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genAddressReg(os);
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os << std::endl;
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}
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void Instruction::h_FSQRT_R(std::ostream& os) const {
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auto dstIndex = dst % RegisterCountFlt;
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os << "e" << dstIndex << std::endl;
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}
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void Instruction::h_CFROUND(std::ostream& os) const {
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os << "r" << (int)src << ", " << (getImm32() & 63) << std::endl;
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}
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static inline const char* condition(int index) {
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switch (index)
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{
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case 0:
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return "be";
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case 1:
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return "ab";
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case 2:
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return "sg";
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case 3:
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return "ns";
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case 4:
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return "of";
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case 5:
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return "no";
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case 6:
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return "lt";
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case 7:
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return "ge";
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default:
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UNREACHABLE;
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}
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}
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void Instruction::h_CBRANCH(std::ostream& os) const {
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os << (int32_t)getImm32() << ", COND " << (int)(getModCond()) << std::endl;
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}
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void Instruction::h_ISTORE(std::ostream& os) const {
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genAddressRegDst(os);
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os << ", r" << (int)src << std::endl;
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}
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void Instruction::h_NOP(std::ostream& os) const {
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os << std::endl;
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}
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#include "instruction_weights.hpp"
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#define INST_NAME(x) REPN(#x, WT(x))
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#define INST_HANDLE(x) REPN(&Instruction::h_##x, WT(x))
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const char* Instruction::names[256] = {
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INST_NAME(IADD_RS)
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INST_NAME(IADD_M)
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INST_NAME(ISUB_R)
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INST_NAME(ISUB_M)
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INST_NAME(IMUL_R)
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INST_NAME(IMUL_M)
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INST_NAME(IMULH_R)
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INST_NAME(IMULH_M)
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INST_NAME(ISMULH_R)
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INST_NAME(ISMULH_M)
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INST_NAME(IMUL_RCP)
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INST_NAME(INEG_R)
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INST_NAME(IXOR_R)
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INST_NAME(IXOR_M)
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INST_NAME(IROR_R)
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INST_NAME(ISWAP_R)
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INST_NAME(FSWAP_R)
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INST_NAME(FADD_R)
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INST_NAME(FADD_M)
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INST_NAME(FSUB_R)
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INST_NAME(FSUB_M)
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INST_NAME(FSCAL_R)
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INST_NAME(FMUL_R)
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INST_NAME(FDIV_M)
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INST_NAME(FSQRT_R)
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INST_NAME(CBRANCH)
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INST_NAME(CFROUND)
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INST_NAME(ISTORE)
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INST_NAME(NOP)
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};
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InstructionFormatter Instruction::engine[256] = {
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INST_HANDLE(IADD_RS)
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INST_HANDLE(IADD_M)
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INST_HANDLE(ISUB_R)
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INST_HANDLE(ISUB_M)
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INST_HANDLE(IMUL_R)
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INST_HANDLE(IMUL_M)
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INST_HANDLE(IMULH_R)
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INST_HANDLE(IMULH_M)
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INST_HANDLE(ISMULH_R)
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INST_HANDLE(ISMULH_M)
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INST_HANDLE(IMUL_RCP)
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INST_HANDLE(INEG_R)
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INST_HANDLE(IXOR_R)
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INST_HANDLE(IXOR_M)
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INST_HANDLE(IROR_R)
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INST_HANDLE(IROL_R)
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INST_HANDLE(ISWAP_R)
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INST_HANDLE(FSWAP_R)
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INST_HANDLE(FADD_R)
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INST_HANDLE(FADD_M)
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INST_HANDLE(FSUB_R)
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INST_HANDLE(FSUB_M)
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INST_HANDLE(FSCAL_R)
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INST_HANDLE(FMUL_R)
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INST_HANDLE(FDIV_M)
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INST_HANDLE(FSQRT_R)
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INST_HANDLE(CBRANCH)
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INST_HANDLE(CFROUND)
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INST_HANDLE(ISTORE)
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INST_HANDLE(NOP)
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};
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} |