Commit Graph

20 Commits

Author SHA1 Message Date
tevador d7eefce583 Removed capital letters from filenames 2019-04-20 16:53:06 +02:00
tevador 682000b1a9 Unique scratchpad addresses - interpreter
Additional writes to L3
2019-04-16 18:58:44 +02:00
tevador 174754cb2b Added branches - ASM and JIT only 2019-03-17 23:09:11 +01:00
tevador e65d9da66c Configurable parameters separated into configuration.h 2019-03-08 15:34:34 +01:00
tevador f3b114af88 Replaced division instructions with IMUL_RCP 2019-02-22 17:48:26 +01:00
tevador f76e8c2e20 Reworked "FNEG" instruction to make ASIC optimizations more difficult 2019-02-13 00:01:34 +01:00
tevador 32d827d0a6 Interpreter with bytecode
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
2019-02-09 15:45:26 +01:00
tevador a586751f6b Removed FPNEG instruction
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
2019-02-07 16:11:27 +01:00
tevador ac4462ad42 Renamed floating point instructions
Fixed negative source operand for FMUL_M and FDIV_M
2019-02-05 23:43:57 +01:00
tevador b417fd08ea 16 -> 8 chained programs
constant address loads are always from L3
2019-02-05 23:06:44 +01:00
tevador 1ee94bef2a Added ISWAP instruction
Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
2019-02-04 17:07:00 +01:00
tevador 8f2abd6c05 NOP instruction
register load/store from L3
2019-01-27 18:19:49 +01:00
tevador 005c67f64c Added explicit STORE instructions
JIT compiler
2019-01-27 10:52:30 +01:00
tevador d2cb086221 ASM code generator for "small" programs that fit into the uOP cache 2019-01-24 19:29:59 +01:00
tevador 1426fcbab5 Print average program code size
Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
2019-01-12 16:05:09 +01:00
tevador 2756bcdcfe Added magic division to JIT compiler
New B operand selection rules
2019-01-11 16:53:52 +01:00
tevador 557241cd95 JUMP instruction 2019-01-11 09:58:06 +01:00
tevador 3caecc7646 Vector FPU instructions
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
2018-12-31 19:06:45 +01:00
tevador 740c40b218 8 branch conditions for CALL/RET 2018-12-21 22:41:35 +01:00
tevador c9102ee88c RandomX portable interpreter 2018-12-11 21:00:30 +01:00