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Code Issues Projects Releases Wiki Activity
188 commits 8 branches 5 tags 3.3 MiB
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26 commits

Author SHA1 Message Date
tevador
d7276d5786 Reduced the number of virtual calls per hash 2019-04-20 12:49:24 +02:00
tevador
296e77eebc C API - first working version 2019-04-20 11:08:01 +02:00
tevador
67046a9f38 Full-width mantissa for group E registers and FDIV_M 2019-04-17 16:18:02 +02:00
tevador
8c37d4aac3 More refactoring 2019-04-12 19:36:08 +02:00
tevador
b4c02051fa Reworked SuperscalarHash instruction set 
ASM and C code generator for SuperscalarHash
Support for Superscalar hash in the light mode
 2019-04-07 15:38:51 +02:00
tevador
2edf05cedc Implemented Dataset size increase per epoch 2019-03-10 23:14:03 +01:00
tevador
e65d9da66c Configurable parameters separated into configuration.h 2019-03-08 15:34:34 +01:00
tevador
219efce06c New command line options 2019-02-19 22:47:45 +01:00
tevador
2798d78717 Render imm32 as signed in RandomX code 2019-02-09 16:19:15 +01:00
tevador
32d827d0a6 Interpreter with bytecode 
Fixed some undefined behavior with signed types
Fixed different results on big endian systems
Removed unused code files
Restored FNEG_R instructions
Updated documentation
 2019-02-09 15:45:26 +01:00
tevador
a586751f6b Removed FPNEG instruction 
Optimized instruction frequencies
Increased the range for A registers from [1,65536) to [1, 4294967296)
 2019-02-07 16:11:27 +01:00
tevador
1ee94bef2a Added ISWAP instruction 
Scratchpad -> 2 MiB
New scratchpad initialization
New dataset initialization
 2019-02-04 17:07:00 +01:00
tevador
005c67f64c Added explicit STORE instructions 
JIT compiler
 2019-01-27 10:52:30 +01:00
tevador
d2cb086221 ASM code generator for "small" programs that fit into the uOP cache 2019-01-24 19:29:59 +01:00
tevador
bd0dba88a8 4 scratchpad segments 2019-01-20 00:44:01 +01:00
tevador
8b1102ee05 Interpreter + async mode 2019-01-15 00:01:11 +01:00
tevador
1426fcbab5 Print average program code size 
Fixed assembly for MUL_64 and IMUL_32
Division weight 4 -> 8
 2019-01-12 16:05:09 +01:00
tevador
d1a808643d Random accesses - JIT compiler 2019-01-10 22:04:55 +01:00
tevador
619bee5418 Random dataset accesses - asm only 
Initial support for large pages
 2019-01-04 19:44:15 +01:00
tevador
3caecc7646 Vector FPU instructions 
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
 2018-12-31 19:06:45 +01:00
tevador
55afe9646f Debuggable assembly generator 2018-12-21 21:09:55 +01:00
tevador
b9d2d853aa Support for multiple threads 2018-12-19 21:54:44 +01:00
tevador
ed0bc906d6 JIT compiler for x86 2018-12-18 22:00:58 +01:00
tevador
ddc29cb4d3 Optimized x86 initialization 2018-12-16 15:10:03 +01:00
tevador
6332831ec1 Implemented cache shift 
Fixed assembly code generator
Fixed an error in the interpreter
Updated specification: sign-extended immediates
 2018-12-15 23:13:17 +01:00
tevador
cb0721056a Assembly code generator for Windows 64-bit 2018-12-13 23:11:55 +01:00