18 commits

Author	SHA1	Message	Date
tevador	ab859879a2	loop body = 128 instructions	2019-01-27 20:10:03 +01:00
tevador	7c049cce8d	Added store instructions	2019-01-24 21:49:39 +01:00
tevador	5b7df0c5e1	Test ASM for a new program structure	2019-01-24 19:35:11 +01:00
tevador	072130c774	ALU/FPU test: Fixed MSVC x86 build	2018-11-20 22:41:34 +01:00
tevador	f19995d4c5	ALU and FPU tests	2018-11-19 22:53:19 +01:00
tevador	1cc4fda4e7	Improved DRAM random access address space	2018-11-16 19:05:18 +01:00
tevador	d3739015ea	Fixed random read frequency	2018-11-16 18:12:32 +01:00
tevador	9ed71ae167	New DRAM reading pattern ... New instruction weights	2018-11-16 16:35:17 +01:00
tevador	58ae98c6a4	Fixed clang compilation	2018-11-14 22:41:51 +01:00
tevador	df9180a30b	Performance benchmark for x86	2018-11-14 20:17:44 +01:00
tevador	1ca1046c57	Fixed unaligned memory errors	2018-11-11 18:22:52 +01:00
tevador	71bf9bd096	Fixed a possible type error in python	2018-11-11 13:59:17 +01:00
tevador	8f3b145fe6	Added DRAM buffer option to rx2c	2018-11-11 13:05:34 +01:00
tevador	2ea440d0f5	New instruction encoding	2018-11-10 22:25:51 +01:00
tevador	cf59ced795	RandomX C generator ... Updated specification	2018-11-09 21:05:45 +01:00
tevador	5114d6b5fe	Updated specification	2018-11-04 19:42:19 +01:00
tevador	d69d3d69a0	Fixed a bug in predictable branching	2018-11-04 15:38:19 +01:00
tevador	8a81aa6453	Branch prediction test programs	2018-11-04 14:38:02 +01:00