16 commits

Author	SHA1	Message	Date
tevador	f3b114af88	Replaced division instructions with IMUL_RCP	2019-02-22 17:48:26 +01:00
tevador	f76e8c2e20	Reworked "FNEG" instruction to make ASIC optimizations more difficult	2019-02-13 00:01:34 +01:00
tevador	b8ce504be6	Added comments to hashAes1Rx4 and fillAes1Rx4 ... Fixed gcc compilation Added performance numbers	2019-02-09 19:32:53 +01:00
tevador	32d827d0a6	Interpreter with bytecode ... Fixed some undefined behavior with signed types Fixed different results on big endian systems Removed unused code files Restored FNEG_R instructions Updated documentation	2019-02-09 15:45:26 +01:00
tevador	a586751f6b	Removed FPNEG instruction ... Optimized instruction frequencies Increased the range for A registers from [1,65536) to [1, 4294967296)	2019-02-07 16:11:27 +01:00
tevador	ac4462ad42	Renamed floating point instructions ... Fixed negative source operand for FMUL_M and FDIV_M	2019-02-05 23:43:57 +01:00
tevador	1ee94bef2a	Added ISWAP instruction ... Scratchpad -> 2 MiB New scratchpad initialization New dataset initialization	2019-02-04 17:07:00 +01:00
tevador	8f2abd6c05	NOP instruction ... register load/store from L3	2019-01-27 18:19:49 +01:00
tevador	005c67f64c	Added explicit STORE instructions ... JIT compiler	2019-01-27 10:52:30 +01:00
tevador	48d85643de	Dataset intialization algorithm (AES)	2019-01-13 13:47:25 +01:00
tevador	1426fcbab5	Print average program code size ... Fixed assembly for MUL_64 and IMUL_32 Division weight 4 -> 8	2019-01-12 16:05:09 +01:00
tevador	2756bcdcfe	Added magic division to JIT compiler ... New B operand selection rules	2019-01-11 16:53:52 +01:00
tevador	557241cd95	JUMP instruction	2019-01-11 09:58:06 +01:00
tevador	d1a808643d	Random accesses - JIT compiler	2019-01-10 22:04:55 +01:00
tevador	3caecc7646	Vector FPU instructions ... JitCompilerX86 - static code written in asm Updated ALU/FPU tests Updated instruction weights	2018-12-31 19:06:45 +01:00
tevador	ed0bc906d6	JIT compiler for x86	2018-12-18 22:00:58 +01:00