tevador
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20eb549725
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Merged load/store of integer and FP registers
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2019-01-27 19:33:55 +01:00 |
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tevador
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005c67f64c
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Added explicit STORE instructions
JIT compiler
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2019-01-27 10:52:30 +01:00 |
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tevador
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a7ffe8c19a
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Mix dataset cacheline with registers r0-r7
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2019-01-13 21:14:59 +01:00 |
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tevador
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67e741ff22
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Reduced x86 code size by 512 bytes (and ecx -> and eax)
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2019-01-12 20:27:35 +01:00 |
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tevador
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d1a808643d
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Random accesses - JIT compiler
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2019-01-10 22:04:55 +01:00 |
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tevador
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3caecc7646
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Vector FPU instructions
JitCompilerX86 - static code written in asm
Updated ALU/FPU tests
Updated instruction weights
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2018-12-31 19:06:45 +01:00 |