13 commits

Author	SHA1	Message	Date
tevador	b8ce504be6	Added comments to hashAes1Rx4 and fillAes1Rx4 ... Fixed gcc compilation Added performance numbers	2019-02-09 19:32:53 +01:00
tevador	2798d78717	Render imm32 as signed in RandomX code	2019-02-09 16:19:15 +01:00
tevador	32d827d0a6	Interpreter with bytecode ... Fixed some undefined behavior with signed types Fixed different results on big endian systems Removed unused code files Restored FNEG_R instructions Updated documentation	2019-02-09 15:45:26 +01:00
tevador	a586751f6b	Removed FPNEG instruction ... Optimized instruction frequencies Increased the range for A registers from [1,65536) to [1, 4294967296)	2019-02-07 16:11:27 +01:00
tevador	ac4462ad42	Renamed floating point instructions ... Fixed negative source operand for FMUL_M and FDIV_M	2019-02-05 23:43:57 +01:00
tevador	b417fd08ea	16 -> 8 chained programs ... constant address loads are always from L3	2019-02-05 23:06:44 +01:00
tevador	1ee94bef2a	Added ISWAP instruction ... Scratchpad -> 2 MiB New scratchpad initialization New dataset initialization	2019-02-04 17:07:00 +01:00
tevador	8f2abd6c05	NOP instruction ... register load/store from L3	2019-01-27 18:19:49 +01:00
tevador	005c67f64c	Added explicit STORE instructions ... JIT compiler	2019-01-27 10:52:30 +01:00
tevador	d2cb086221	ASM code generator for "small" programs that fit into the uOP cache	2019-01-24 19:29:59 +01:00
tevador	557241cd95	JUMP instruction	2019-01-11 09:58:06 +01:00
tevador	1db7dd6e8b	Renamed immediate constants	2018-12-20 18:36:09 +01:00
tevador	cb0721056a	Assembly code generator for Windows 64-bit	2018-12-13 23:11:55 +01:00