15 commits

Author	SHA1	Message	Date
tevador	32d827d0a6	Interpreter with bytecode ... Fixed some undefined behavior with signed types Fixed different results on big endian systems Removed unused code files Restored FNEG_R instructions Updated documentation	2019-02-09 15:45:26 +01:00
tevador	a586751f6b	Removed FPNEG instruction ... Optimized instruction frequencies Increased the range for A registers from [1,65536) to [1, 4294967296)	2019-02-07 16:11:27 +01:00
tevador	ac4462ad42	Renamed floating point instructions ... Fixed negative source operand for FMUL_M and FDIV_M	2019-02-05 23:43:57 +01:00
tevador	1ee94bef2a	Added ISWAP instruction ... Scratchpad -> 2 MiB New scratchpad initialization New dataset initialization	2019-02-04 17:07:00 +01:00
tevador	8f2abd6c05	NOP instruction ... register load/store from L3	2019-01-27 18:19:49 +01:00
tevador	005c67f64c	Added explicit STORE instructions ... JIT compiler	2019-01-27 10:52:30 +01:00
tevador	d2cb086221	ASM code generator for "small" programs that fit into the uOP cache	2019-01-24 19:29:59 +01:00
tevador	2756bcdcfe	Added magic division to JIT compiler ... New B operand selection rules	2019-01-11 16:53:52 +01:00
tevador	557241cd95	JUMP instruction	2019-01-11 09:58:06 +01:00
tevador	d1a808643d	Random accesses - JIT compiler	2019-01-10 22:04:55 +01:00
tevador	b71e0eec65	Optimizations to reduce code size under 32K	2019-01-08 14:50:31 +01:00
tevador	2f6a599ff6	Inlined calls for memory read	2019-01-07 17:44:43 +01:00
tevador	619bee5418	Random dataset accesses - asm only ... Initial support for large pages	2019-01-04 19:44:15 +01:00
tevador	3caecc7646	Vector FPU instructions ... JitCompilerX86 - static code written in asm Updated ALU/FPU tests Updated instruction weights	2018-12-31 19:06:45 +01:00
tevador	cb0721056a	Assembly code generator for Windows 64-bit	2018-12-13 23:11:55 +01:00