mirror of
https://git.wownero.com/wownero/RandomWOW.git
synced 2024-08-15 00:23:14 +00:00
SChernykh
tevador
parent
5fb26fc607
commit
c6468a3816
8 changed files with 1794 additions and 28 deletions
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@ -116,6 +116,12 @@ endif()
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# ARMv8
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if (ARM_ID STREQUAL "aarch64" OR ARM_ID STREQUAL "arm64" OR ARM_ID STREQUAL "armv8-a")
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list(APPEND randomx_sources
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src/jit_compiler_a64_static.S
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src/jit_compiler_a64.cpp)
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# cheat because cmake and ccache hate each other
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set_property(SOURCE src/jit_compiler_a64_static.S PROPERTY LANGUAGE C)
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if(ARCH STREQUAL "native")
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add_flag("-march=native")
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else()
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@ -119,7 +119,7 @@ namespace randomx {
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class JitCompilerX86;
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using JitCompiler = JitCompilerX86;
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#elif defined(__aarch64__)
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#define RANDOMX_HAVE_COMPILER 0
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#define RANDOMX_HAVE_COMPILER 1
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class JitCompilerA64;
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using JitCompiler = JitCompilerA64;
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#else
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@ -385,7 +385,14 @@ FORCE_INLINE rx_vec_f128 rx_cvt_packed_int_vec_f128(const void* addr) {
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typedef uint8x16_t rx_vec_i128;
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typedef float64x2_t rx_vec_f128;
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#define rx_aligned_alloc(size, align) aligned_alloc(align, size)
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inline void* rx_aligned_alloc(size_t size, size_t align) {
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void* p;
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if (posix_memalign(&p, align, size) == 0)
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return p;
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return 0;
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};
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#define rx_aligned_free(a) free(a)
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inline void rx_prefetch_nta(void* ptr) {
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1068
src/jit_compiler_a64.cpp
Normal file
1068
src/jit_compiler_a64.cpp
Normal file
File diff suppressed because it is too large
Load diff
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@ -1,5 +1,6 @@
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/*
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Copyright (c) 2018-2019, tevador <tevador@gmail.com>
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Copyright (c) 2019, SChernykh <https://github.com/SChernykh>
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All rights reserved.
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@ -32,45 +33,96 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <vector>
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#include <stdexcept>
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#include "common.hpp"
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#include "jit_compiler_a64_static.hpp"
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namespace randomx {
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class Program;
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class ProgramConfiguration;
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class SuperscalarProgram;
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class Instruction;
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typedef void(JitCompilerA64::*InstructionGeneratorA64)(Instruction&, uint32_t&);
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class JitCompilerA64 {
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public:
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JitCompilerA64() {
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throw std::runtime_error("ARM64 JIT compiler is not implemented yet.");
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}
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void generateProgram(Program&, ProgramConfiguration&) {
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JitCompilerA64();
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~JitCompilerA64();
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void generateProgram(Program&, ProgramConfiguration&);
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void generateProgramLight(Program&, ProgramConfiguration&, uint32_t);
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}
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void generateProgramLight(Program&, ProgramConfiguration&, uint32_t) {
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}
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template<size_t N>
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void generateSuperscalarHash(SuperscalarProgram(&programs)[N], std::vector<uint64_t> &) {
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void generateSuperscalarHash(SuperscalarProgram(&programs)[N], std::vector<uint64_t> &);
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}
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void generateDatasetInitCode() {
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void generateDatasetInitCode() {}
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ProgramFunc* getProgramFunc() { return reinterpret_cast<ProgramFunc*>(code); }
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DatasetInitFunc* getDatasetInitFunc();
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uint8_t* getCode() { return code; }
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size_t getCodeSize();
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void enableWriting();
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void enableExecution();
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void enableAll();
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private:
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static InstructionGeneratorA64 engine[256];
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uint32_t reg_changed_offset[8];
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uint8_t* code;
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uint32_t literalPos;
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uint32_t num32bitLiterals;
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static void emit32(uint32_t val, uint8_t* code, uint32_t& codePos)
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{
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*(uint32_t*)(code + codePos) = val;
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codePos += sizeof(val);
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}
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ProgramFunc* getProgramFunc() {
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return nullptr;
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static void emit64(uint64_t val, uint8_t* code, uint32_t& codePos)
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{
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*(uint64_t*)(code + codePos) = val;
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codePos += sizeof(val);
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}
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DatasetInitFunc* getDatasetInitFunc() {
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return nullptr;
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}
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uint8_t* getCode() {
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return nullptr;
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}
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size_t getCodeSize() {
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return 0;
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}
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void enableWriting() {}
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void enableExecution() {}
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void enableAll() {}
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void emitMovImmediate(uint32_t dst, uint32_t imm, uint8_t* code, uint32_t& codePos);
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void emitAddImmediate(uint32_t dst, uint32_t src, uint32_t imm, uint8_t* code, uint32_t& codePos);
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template<uint32_t tmp_reg>
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void emitMemLoad(uint32_t dst, uint32_t src, Instruction& instr, uint8_t* code, uint32_t& codePos);
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template<uint32_t tmp_reg_fp>
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void emitMemLoadFP(uint32_t src, Instruction& instr, uint8_t* code, uint32_t& codePos);
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void h_IADD_RS(Instruction&, uint32_t&);
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void h_IADD_M(Instruction&, uint32_t&);
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void h_ISUB_R(Instruction&, uint32_t&);
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void h_ISUB_M(Instruction&, uint32_t&);
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void h_IMUL_R(Instruction&, uint32_t&);
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void h_IMUL_M(Instruction&, uint32_t&);
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void h_IMULH_R(Instruction&, uint32_t&);
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void h_IMULH_M(Instruction&, uint32_t&);
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void h_ISMULH_R(Instruction&, uint32_t&);
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void h_ISMULH_M(Instruction&, uint32_t&);
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void h_IMUL_RCP(Instruction&, uint32_t&);
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void h_INEG_R(Instruction&, uint32_t&);
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void h_IXOR_R(Instruction&, uint32_t&);
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void h_IXOR_M(Instruction&, uint32_t&);
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void h_IROR_R(Instruction&, uint32_t&);
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void h_IROL_R(Instruction&, uint32_t&);
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void h_ISWAP_R(Instruction&, uint32_t&);
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void h_FSWAP_R(Instruction&, uint32_t&);
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void h_FADD_R(Instruction&, uint32_t&);
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void h_FADD_M(Instruction&, uint32_t&);
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void h_FSUB_R(Instruction&, uint32_t&);
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void h_FSUB_M(Instruction&, uint32_t&);
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void h_FSCAL_R(Instruction&, uint32_t&);
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void h_FMUL_R(Instruction&, uint32_t&);
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void h_FDIV_M(Instruction&, uint32_t&);
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void h_FSQRT_R(Instruction&, uint32_t&);
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void h_CBRANCH(Instruction&, uint32_t&);
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void h_CFROUND(Instruction&, uint32_t&);
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void h_ISTORE(Instruction&, uint32_t&);
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void h_NOP(Instruction&, uint32_t&);
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};
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}
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}
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579
src/jit_compiler_a64_static.S
Normal file
579
src/jit_compiler_a64_static.S
Normal file
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@ -0,0 +1,579 @@
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# Copyright (c) 2018-2019, tevador <tevador@gmail.com>
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# Copyright (c) 2019, SChernykh <https://github.com/SChernykh>
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#
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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# * Neither the name of the copyright holder nor the
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# names of its contributors may be used to endorse or promote products
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# derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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.arch armv8-a
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.text
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.global randomx_program_aarch64
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.global randomx_program_aarch64_main_loop
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.global randomx_program_aarch64_vm_instructions
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.global randomx_program_aarch64_imul_rcp_literals_end
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.global randomx_program_aarch64_vm_instructions_end
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.global randomx_program_aarch64_cacheline_align_mask1
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.global randomx_program_aarch64_cacheline_align_mask2
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.global randomx_program_aarch64_update_spMix1
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.global randomx_program_aarch64_vm_instructions_end_light
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.global randomx_program_aarch64_light_cacheline_align_mask
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.global randomx_program_aarch64_light_dataset_offset
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.global randomx_init_dataset_aarch64
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.global randomx_init_dataset_aarch64_end
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.global randomx_calc_dataset_item_aarch64
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.global randomx_calc_dataset_item_aarch64_prefetch
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.global randomx_calc_dataset_item_aarch64_mix
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.global randomx_calc_dataset_item_aarch64_store_result
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.global randomx_calc_dataset_item_aarch64_end
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#include "configuration.h"
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# Register allocation
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# x0 -> pointer to reg buffer and then literal for IMUL_RCP
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# x1 -> pointer to mem buffer and then to dataset
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# x2 -> pointer to scratchpad
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# x3 -> loop counter
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# x4 -> "r0"
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# x5 -> "r1"
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# x6 -> "r2"
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# x7 -> "r3"
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# x8 -> fpcr (reversed bits)
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# x9 -> mx, ma
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# x10 -> spMix1
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# x11 -> literal for IMUL_RCP
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# x12 -> "r4"
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# x13 -> "r5"
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# x14 -> "r6"
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# x15 -> "r7"
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# x16 -> spAddr0
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# x17 -> spAddr1
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# x18 -> temporary
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# x19 -> temporary
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# x20 -> literal for IMUL_RCP
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# x21 -> literal for IMUL_RCP
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# x22 -> literal for IMUL_RCP
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# x23 -> literal for IMUL_RCP
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# x24 -> literal for IMUL_RCP
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# x25 -> literal for IMUL_RCP
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# x26 -> literal for IMUL_RCP
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# x27 -> literal for IMUL_RCP
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# x28 -> literal for IMUL_RCP
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# x29 -> literal for IMUL_RCP
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# x30 -> literal for IMUL_RCP
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# v0-v15 -> store 32-bit literals
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# v16 -> "f0"
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# v17 -> "f1"
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# v18 -> "f2"
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# v19 -> "f3"
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# v20 -> "e0"
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# v21 -> "e1"
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# v22 -> "e2"
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# v23 -> "e3"
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# v24 -> "a0"
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# v25 -> "a1"
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# v26 -> "a2"
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# v27 -> "a3"
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# v28 -> temporary
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# v29 -> E 'and' mask = 0x00ffffffffffffff00ffffffffffffff
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# v30 -> E 'or' mask = 0x3*00000000******3*00000000******
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# v31 -> scale mask = 0x81f000000000000081f0000000000000
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randomx_program_aarch64:
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# Save callee-saved registers
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sub sp, sp, 192
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stp x16, x17, [sp]
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stp x18, x19, [sp, 16]
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stp x20, x21, [sp, 32]
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stp x22, x23, [sp, 48]
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stp x24, x25, [sp, 64]
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stp x26, x27, [sp, 80]
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stp x28, x29, [sp, 96]
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stp x8, x30, [sp, 112]
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stp d8, d9, [sp, 128]
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stp d10, d11, [sp, 144]
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stp d12, d13, [sp, 160]
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stp d14, d15, [sp, 176]
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# Zero integer registers
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mov x4, xzr
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mov x5, xzr
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mov x6, xzr
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mov x7, xzr
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mov x12, xzr
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mov x13, xzr
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mov x14, xzr
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mov x15, xzr
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# Load ma, mx and dataset pointer
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ldp x9, x1, [x1]
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# Load initial spMix value
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mov x10, x9
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# Load group A registers
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ldp q24, q25, [x0, 192]
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ldp q26, q27, [x0, 224]
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# Load E 'and' mask
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mov x16, 0x00FFFFFFFFFFFFFF
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ins v29.d[0], x16
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ins v29.d[1], x16
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# Load E 'or' mask (stored in reg.f[0])
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ldr q30, [x0, 64]
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# Load scale mask
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mov x16, 0x80f0000000000000
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ins v31.d[0], x16
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ins v31.d[1], x16
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# Read fpcr
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mrs x8, fpcr
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rbit x8, x8
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# Save x0
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str x0, [sp, -16]!
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# Read literals
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ldr x0, literal_x0
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ldr x11, literal_x11
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ldr x20, literal_x20
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ldr x21, literal_x21
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ldr x22, literal_x22
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ldr x23, literal_x23
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ldr x24, literal_x24
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ldr x25, literal_x25
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ldr x26, literal_x26
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ldr x27, literal_x27
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ldr x28, literal_x28
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ldr x29, literal_x29
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ldr x30, literal_x30
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ldr q0, literal_v0
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ldr q1, literal_v1
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ldr q2, literal_v2
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ldr q3, literal_v3
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ldr q4, literal_v4
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ldr q5, literal_v5
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ldr q6, literal_v6
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ldr q7, literal_v7
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ldr q8, literal_v8
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ldr q9, literal_v9
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ldr q10, literal_v10
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ldr q11, literal_v11
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ldr q12, literal_v12
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ldr q13, literal_v13
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ldr q14, literal_v14
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ldr q15, literal_v15
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randomx_program_aarch64_main_loop:
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# spAddr0 = spMix1 & ScratchpadL3Mask64;
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# spAddr1 = (spMix1 >> 32) & ScratchpadL3Mask64;
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lsr x18, x10, 32
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# Actual mask will be inserted by JIT compiler
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and w16, w10, 1
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and w17, w18, 1
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# x16 = scratchpad + spAddr0
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# x17 = scratchpad + spAddr1
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add x16, x16, x2
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add x17, x17, x2
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# xor integer registers with scratchpad data (spAddr0)
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ldp x18, x19, [x16]
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eor x4, x4, x18
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eor x5, x5, x19
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ldp x18, x19, [x16, 16]
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eor x6, x6, x18
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eor x7, x7, x19
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ldp x18, x19, [x16, 32]
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eor x12, x12, x18
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eor x13, x13, x19
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ldp x18, x19, [x16, 48]
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eor x14, x14, x18
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eor x15, x15, x19
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# Load group F registers (spAddr1)
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ldpsw x18, x19, [x17]
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ins v16.d[0], x18
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ins v16.d[1], x19
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ldpsw x18, x19, [x17, 8]
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ins v17.d[0], x18
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ins v17.d[1], x19
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ldpsw x18, x19, [x17, 16]
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ins v18.d[0], x18
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ins v18.d[1], x19
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ldpsw x18, x19, [x17, 24]
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ins v19.d[0], x18
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ins v19.d[1], x19
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scvtf v16.2d, v16.2d
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scvtf v17.2d, v17.2d
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scvtf v18.2d, v18.2d
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scvtf v19.2d, v19.2d
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# Load group E registers (spAddr1)
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ldpsw x18, x19, [x17, 32]
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ins v20.d[0], x18
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ins v20.d[1], x19
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ldpsw x18, x19, [x17, 40]
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ins v21.d[0], x18
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ins v21.d[1], x19
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ldpsw x18, x19, [x17, 48]
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ins v22.d[0], x18
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ins v22.d[1], x19
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ldpsw x18, x19, [x17, 56]
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ins v23.d[0], x18
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ins v23.d[1], x19
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scvtf v20.2d, v20.2d
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scvtf v21.2d, v21.2d
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scvtf v22.2d, v22.2d
|
||||
scvtf v23.2d, v23.2d
|
||||
and v20.16b, v20.16b, v29.16b
|
||||
and v21.16b, v21.16b, v29.16b
|
||||
and v22.16b, v22.16b, v29.16b
|
||||
and v23.16b, v23.16b, v29.16b
|
||||
orr v20.16b, v20.16b, v30.16b
|
||||
orr v21.16b, v21.16b, v30.16b
|
||||
orr v22.16b, v22.16b, v30.16b
|
||||
orr v23.16b, v23.16b, v30.16b
|
||||
|
||||
# Execute VM instructions
|
||||
randomx_program_aarch64_vm_instructions:
|
||||
|
||||
# buffer for generated instructions
|
||||
# FDIV_M is the largest instruction taking up to 12 ARMv8 instructions
|
||||
.fill RANDOMX_PROGRAM_SIZE*12,4,0
|
||||
|
||||
literal_x0: .fill 1,8,0
|
||||
literal_x11: .fill 1,8,0
|
||||
literal_x20: .fill 1,8,0
|
||||
literal_x21: .fill 1,8,0
|
||||
literal_x22: .fill 1,8,0
|
||||
literal_x23: .fill 1,8,0
|
||||
literal_x24: .fill 1,8,0
|
||||
literal_x25: .fill 1,8,0
|
||||
literal_x26: .fill 1,8,0
|
||||
literal_x27: .fill 1,8,0
|
||||
literal_x28: .fill 1,8,0
|
||||
literal_x29: .fill 1,8,0
|
||||
literal_x30: .fill 1,8,0
|
||||
randomx_program_aarch64_imul_rcp_literals_end:
|
||||
|
||||
literal_v0: .fill 2,8,0
|
||||
literal_v1: .fill 2,8,0
|
||||
literal_v2: .fill 2,8,0
|
||||
literal_v3: .fill 2,8,0
|
||||
literal_v4: .fill 2,8,0
|
||||
literal_v5: .fill 2,8,0
|
||||
literal_v6: .fill 2,8,0
|
||||
literal_v7: .fill 2,8,0
|
||||
literal_v8: .fill 2,8,0
|
||||
literal_v9: .fill 2,8,0
|
||||
literal_v10: .fill 2,8,0
|
||||
literal_v11: .fill 2,8,0
|
||||
literal_v12: .fill 2,8,0
|
||||
literal_v13: .fill 2,8,0
|
||||
literal_v14: .fill 2,8,0
|
||||
literal_v15: .fill 2,8,0
|
||||
|
||||
randomx_program_aarch64_vm_instructions_end:
|
||||
|
||||
# mx ^= r[readReg2] ^ r[readReg3];
|
||||
eor x9, x9, x18
|
||||
|
||||
# Calculate dataset pointer for dataset prefetch
|
||||
mov w18, w9
|
||||
randomx_program_aarch64_cacheline_align_mask1:
|
||||
# Actual mask will be inserted by JIT compiler
|
||||
and x18, x18, 1
|
||||
add x18, x18, x1
|
||||
|
||||
# Prefetch dataset data
|
||||
prfm pldl2strm, [x18]
|
||||
|
||||
# mx <-> ma
|
||||
ror x9, x9, 32
|
||||
|
||||
# Calculate dataset pointer for dataset read
|
||||
mov w10, w9
|
||||
randomx_program_aarch64_cacheline_align_mask2:
|
||||
# Actual mask will be inserted by JIT compiler
|
||||
and x10, x10, 1
|
||||
add x10, x10, x1
|
||||
|
||||
randomx_program_aarch64_xor_with_dataset_line:
|
||||
# xor integer registers with dataset data
|
||||
ldp x18, x19, [x10]
|
||||
eor x4, x4, x18
|
||||
eor x5, x5, x19
|
||||
ldp x18, x19, [x10, 16]
|
||||
eor x6, x6, x18
|
||||
eor x7, x7, x19
|
||||
ldp x18, x19, [x10, 32]
|
||||
eor x12, x12, x18
|
||||
eor x13, x13, x19
|
||||
ldp x18, x19, [x10, 48]
|
||||
eor x14, x14, x18
|
||||
eor x15, x15, x19
|
||||
|
||||
randomx_program_aarch64_update_spMix1:
|
||||
# JIT compiler will replace it with "eor x10, config.readReg0, config.readReg1"
|
||||
eor x10, x0, x0
|
||||
|
||||
# Store integer registers to scratchpad (spAddr1)
|
||||
stp x4, x5, [x17, 0]
|
||||
stp x6, x7, [x17, 16]
|
||||
stp x12, x13, [x17, 32]
|
||||
stp x14, x15, [x17, 48]
|
||||
|
||||
# xor group F and group E registers
|
||||
eor v16.16b, v16.16b, v20.16b
|
||||
eor v17.16b, v17.16b, v21.16b
|
||||
eor v18.16b, v18.16b, v22.16b
|
||||
eor v19.16b, v19.16b, v23.16b
|
||||
|
||||
# Store FP registers to scratchpad (spAddr0)
|
||||
stp q16, q17, [x16, 0]
|
||||
stp q18, q19, [x16, 32]
|
||||
|
||||
subs x3, x3, 1
|
||||
bne randomx_program_aarch64_main_loop
|
||||
|
||||
# Restore x0
|
||||
ldr x0, [sp], 16
|
||||
|
||||
# Store integer registers
|
||||
stp x4, x5, [x0, 0]
|
||||
stp x6, x7, [x0, 16]
|
||||
stp x12, x13, [x0, 32]
|
||||
stp x14, x15, [x0, 48]
|
||||
|
||||
# Store FP registers
|
||||
stp q16, q17, [x0, 64]
|
||||
stp q18, q19, [x0, 96]
|
||||
stp q20, q21, [x0, 128]
|
||||
stp q22, q23, [x0, 160]
|
||||
|
||||
# Restore callee-saved registers
|
||||
ldp x16, x17, [sp]
|
||||
ldp x18, x19, [sp, 16]
|
||||
ldp x20, x21, [sp, 32]
|
||||
ldp x22, x23, [sp, 48]
|
||||
ldp x24, x25, [sp, 64]
|
||||
ldp x26, x27, [sp, 80]
|
||||
ldp x28, x29, [sp, 96]
|
||||
ldp x8, x30, [sp, 112]
|
||||
ldp d8, d9, [sp, 128]
|
||||
ldp d10, d11, [sp, 144]
|
||||
ldp d12, d13, [sp, 160]
|
||||
ldp d14, d15, [sp, 176]
|
||||
add sp, sp, 192
|
||||
|
||||
ret
|
||||
|
||||
randomx_program_aarch64_vm_instructions_end_light:
|
||||
sub sp, sp, 96
|
||||
stp x0, x1, [sp, 64]
|
||||
stp x2, x30, [sp, 80]
|
||||
|
||||
# mx ^= r[readReg2] ^ r[readReg3];
|
||||
eor x9, x9, x18
|
||||
|
||||
# mx <-> ma
|
||||
ror x9, x9, 32
|
||||
|
||||
# x0 -> pointer to cache memory
|
||||
mov x0, x1
|
||||
|
||||
# x1 -> pointer to output
|
||||
mov x1, sp
|
||||
|
||||
randomx_program_aarch64_light_cacheline_align_mask:
|
||||
# Actual mask will be inserted by JIT compiler
|
||||
and w2, w9, 1
|
||||
|
||||
# x2 -> item number
|
||||
lsr x2, x2, 6
|
||||
|
||||
randomx_program_aarch64_light_dataset_offset:
|
||||
# Apply dataset offset (filled in by JIT compiler)
|
||||
add x2, x2, 0
|
||||
add x2, x2, 0
|
||||
|
||||
bl randomx_calc_dataset_item_aarch64
|
||||
|
||||
mov x10, sp
|
||||
ldp x0, x1, [sp, 64]
|
||||
ldp x2, x30, [sp, 80]
|
||||
add sp, sp, 96
|
||||
|
||||
b randomx_program_aarch64_xor_with_dataset_line
|
||||
|
||||
|
||||
|
||||
# Input parameters
|
||||
#
|
||||
# x0 -> pointer to cache
|
||||
# x1 -> pointer to dataset memory at startItem
|
||||
# x2 -> start item
|
||||
# x3 -> end item
|
||||
|
||||
randomx_init_dataset_aarch64:
|
||||
# Save x30 (return address)
|
||||
str x30, [sp, -16]!
|
||||
|
||||
# Load pointer to cache memory
|
||||
ldr x0, [x0]
|
||||
|
||||
randomx_init_dataset_aarch64_main_loop:
|
||||
bl randomx_calc_dataset_item_aarch64
|
||||
add x1, x1, 64
|
||||
add x2, x2, 1
|
||||
cmp x2, x3
|
||||
bne randomx_init_dataset_aarch64_main_loop
|
||||
|
||||
# Restore x30 (return address)
|
||||
ldr x30, [sp], 16
|
||||
|
||||
ret
|
||||
|
||||
randomx_init_dataset_aarch64_end:
|
||||
|
||||
# Input parameters
|
||||
#
|
||||
# x0 -> pointer to cache memory
|
||||
# x1 -> pointer to output
|
||||
# x2 -> item number
|
||||
#
|
||||
# Register allocation
|
||||
#
|
||||
# x0-x7 -> output value (calculated dataset item)
|
||||
# x8 -> pointer to cache memory
|
||||
# x9 -> pointer to output
|
||||
# x10 -> registerValue
|
||||
# x11 -> mixBlock
|
||||
# x12 -> temporary
|
||||
# x13 -> temporary
|
||||
|
||||
randomx_calc_dataset_item_aarch64:
|
||||
sub sp, sp, 112
|
||||
stp x0, x1, [sp]
|
||||
stp x2, x3, [sp, 16]
|
||||
stp x4, x5, [sp, 32]
|
||||
stp x6, x7, [sp, 48]
|
||||
stp x8, x9, [sp, 64]
|
||||
stp x10, x11, [sp, 80]
|
||||
stp x12, x13, [sp, 96]
|
||||
|
||||
mov x8, x0
|
||||
mov x9, x1
|
||||
mov x10, x2
|
||||
|
||||
# rl[0] = (itemNumber + 1) * superscalarMul0;
|
||||
ldr x12, superscalarMul0
|
||||
madd x0, x2, x12, x12
|
||||
|
||||
# rl[1] = rl[0] ^ superscalarAdd1;
|
||||
ldr x12, superscalarAdd1
|
||||
eor x1, x0, x12
|
||||
|
||||
# rl[2] = rl[0] ^ superscalarAdd2;
|
||||
ldr x12, superscalarAdd2
|
||||
eor x2, x0, x12
|
||||
|
||||
# rl[3] = rl[0] ^ superscalarAdd3;
|
||||
ldr x12, superscalarAdd3
|
||||
eor x3, x0, x12
|
||||
|
||||
# rl[4] = rl[0] ^ superscalarAdd4;
|
||||
ldr x12, superscalarAdd4
|
||||
eor x4, x0, x12
|
||||
|
||||
# rl[5] = rl[0] ^ superscalarAdd5;
|
||||
ldr x12, superscalarAdd5
|
||||
eor x5, x0, x12
|
||||
|
||||
# rl[6] = rl[0] ^ superscalarAdd6;
|
||||
ldr x12, superscalarAdd6
|
||||
eor x6, x0, x12
|
||||
|
||||
# rl[7] = rl[0] ^ superscalarAdd7;
|
||||
ldr x12, superscalarAdd7
|
||||
eor x7, x0, x12
|
||||
|
||||
b randomx_calc_dataset_item_aarch64_prefetch
|
||||
|
||||
superscalarMul0: .quad 6364136223846793005
|
||||
superscalarAdd1: .quad 9298411001130361340
|
||||
superscalarAdd2: .quad 12065312585734608966
|
||||
superscalarAdd3: .quad 9306329213124626780
|
||||
superscalarAdd4: .quad 5281919268842080866
|
||||
superscalarAdd5: .quad 10536153434571861004
|
||||
superscalarAdd6: .quad 3398623926847679864
|
||||
superscalarAdd7: .quad 9549104520008361294
|
||||
|
||||
# Prefetch -> SuperScalar hash -> Mix will be repeated N times
|
||||
|
||||
randomx_calc_dataset_item_aarch64_prefetch:
|
||||
# Actual mask will be inserted by JIT compiler
|
||||
and x11, x10, 1
|
||||
add x11, x8, x11, lsl 6
|
||||
prfm pldl2strm, [x11]
|
||||
|
||||
# Generated SuperScalar hash program goes here
|
||||
|
||||
randomx_calc_dataset_item_aarch64_mix:
|
||||
ldp x12, x13, [x11]
|
||||
eor x0, x0, x12
|
||||
eor x1, x1, x13
|
||||
ldp x12, x13, [x11, 16]
|
||||
eor x2, x2, x12
|
||||
eor x3, x3, x13
|
||||
ldp x12, x13, [x11, 32]
|
||||
eor x4, x4, x12
|
||||
eor x5, x5, x13
|
||||
ldp x12, x13, [x11, 48]
|
||||
eor x6, x6, x12
|
||||
eor x7, x7, x13
|
||||
|
||||
randomx_calc_dataset_item_aarch64_store_result:
|
||||
stp x0, x1, [x9]
|
||||
stp x2, x3, [x9, 16]
|
||||
stp x4, x5, [x9, 32]
|
||||
stp x6, x7, [x9, 48]
|
||||
|
||||
ldp x0, x1, [sp]
|
||||
ldp x2, x3, [sp, 16]
|
||||
ldp x4, x5, [sp, 32]
|
||||
ldp x6, x7, [sp, 48]
|
||||
ldp x8, x9, [sp, 64]
|
||||
ldp x10, x11, [sp, 80]
|
||||
ldp x12, x13, [sp, 96]
|
||||
add sp, sp, 112
|
||||
|
||||
ret
|
||||
|
||||
randomx_calc_dataset_item_aarch64_end:
|
||||
51
src/jit_compiler_a64_static.hpp
Normal file
51
src/jit_compiler_a64_static.hpp
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
Copyright (c) 2018-2019, tevador <tevador@gmail.com>
|
||||
Copyright (c) 2019, SChernykh <https://github.com/SChernykh>
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of the copyright holder nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
extern "C" {
|
||||
void randomx_program_aarch64(void* reg, void* mem, void* scratchpad, uint64_t iterations);
|
||||
void randomx_program_aarch64_main_loop();
|
||||
void randomx_program_aarch64_vm_instructions();
|
||||
void randomx_program_aarch64_imul_rcp_literals_end();
|
||||
void randomx_program_aarch64_vm_instructions_end();
|
||||
void randomx_program_aarch64_cacheline_align_mask1();
|
||||
void randomx_program_aarch64_cacheline_align_mask2();
|
||||
void randomx_program_aarch64_update_spMix1();
|
||||
void randomx_program_aarch64_vm_instructions_end_light();
|
||||
void randomx_program_aarch64_light_cacheline_align_mask();
|
||||
void randomx_program_aarch64_light_dataset_offset();
|
||||
void randomx_init_dataset_aarch64();
|
||||
void randomx_init_dataset_aarch64_end();
|
||||
void randomx_calc_dataset_item_aarch64();
|
||||
void randomx_calc_dataset_item_aarch64_prefetch();
|
||||
void randomx_calc_dataset_item_aarch64_mix();
|
||||
void randomx_calc_dataset_item_aarch64_store_result();
|
||||
void randomx_calc_dataset_item_aarch64_end();
|
||||
}
|
||||
|
|
@ -63,6 +63,9 @@ namespace randomx {
|
|||
|
||||
template<class Allocator, bool softAes, bool secureJit>
|
||||
void CompiledVm<Allocator, softAes, secureJit>::execute() {
|
||||
#ifdef __aarch64__
|
||||
memcpy(reg.f, config.eMask, sizeof(config.eMask));
|
||||
#endif
|
||||
compiler.getProgramFunc()(reg, mem, scratchpad, RANDOMX_PROGRAM_ITERATIONS);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue