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Updated documentation and test vectors
Added AesGenerator1R test Added benchmark hints if large pages fail
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5 changed files with 67 additions and 23 deletions
12
doc/specs.md
12
doc/specs.md
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@ -567,8 +567,8 @@ For integer instructions, the destination is always an integer register (registe
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|2/256|INEG_R|R|-|-|`dst = -dst`|
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|15/256|IXOR_R|R|R|`src = imm32`|`dst = dst ^ src`|
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|5/256|IXOR_M|R|R|`src = 0`|`dst = dst ^ [mem]`|
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|10/256|IROR_R|R|R|`src = imm32`|`dst = dst >>> src`|
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|0/256|IROL_R|R|R|`src = imm32`|`dst = dst <<< src`|
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|8/256|IROR_R|R|R|`src = imm32`|`dst = dst >>> src`|
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|2/256|IROL_R|R|R|`src = imm32`|`dst = dst <<< src`|
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|4/256|ISWAP_R|R|R|`src = dst`|`temp = src; src = dst; dst = temp`|
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#### 5.2.1 IADD_RS
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@ -616,13 +616,13 @@ All floating point operations are rounded according to the current value of the
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|frequency|instruction|dst|src|operation|
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|8/256|FSWAP_R|F+E|-|`(dst0, dst1) = (dst1, dst0)`|
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|20/256|FADD_R|F|A|`(dst0, dst1) = (dst0 + src0, dst1 + src1)`|
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|4/256|FSWAP_R|F+E|-|`(dst0, dst1) = (dst1, dst0)`|
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|16/256|FADD_R|F|A|`(dst0, dst1) = (dst0 + src0, dst1 + src1)`|
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|5/256|FADD_M|F|R|`(dst0, dst1) = (dst0 + [mem][0], dst1 + [mem][1])`|
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|20/256|FSUB_R|F|A|`(dst0, dst1) = (dst0 - src0, dst1 - src1)`|
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|16/256|FSUB_R|F|A|`(dst0, dst1) = (dst0 - src0, dst1 - src1)`|
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|5/256|FSUB_M|F|R|`(dst0, dst1) = (dst0 - [mem][0], dst1 - [mem][1])`|
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|6/256|FSCAL_R|F|-|<code>(dst0, dst1) = (-2<sup>x0</sup> * dst0, -2<sup>x1</sup> * dst1)</code>|
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|20/256|FMUL_R|E|A|`(dst0, dst1) = (dst0 * src0, dst1 * src1)`|
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|32/256|FMUL_R|E|A|`(dst0, dst1) = (dst0 * src0, dst1 * src1)`|
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|4/256|FDIV_M|E|R|`(dst0, dst1) = (dst0 / [mem][0], dst1 / [mem][1])`|
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|6/256|FSQRT_R|E|-|`(dst0, dst1) = (√dst0, √dst1)`|
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