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Updated documentation and test vectors

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Added AesGenerator1R test
Added benchmark hints if large pages fail
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tevador 2019-06-22 17:42:26 +02:00
parent 91cd35ff13
commit 8282413154
5 changed files with 67 additions and 23 deletions
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doc/design.md
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@ -157,7 +157,11 @@ The IADD_RS instruction utilizes the address calculation logic of CPUs and can b
Because integer division is not fully pipelined in CPUs and can be made faster in ASICs, the IMUL_RCP instruction requires only one division per program to calculate the reciprocal. This forces an ASIC to include a hardware divider without giving them a performance advantage during program execution.
#### 2.4.3 ISWAP_R
#### 2.4.3 IROR_R/IROL_R
Rotation instructions are split between rotate right and rotate left with a 4:1 ratio. Rotate right has a higher frequency because some architecures (like ARM) don't support rotate left natively (it must be emulated using rotate right).
#### 2.4.4 ISWAP_R
This instruction can be executed efficiently by CPUs that support register renaming/move elimination.