Updated specs: cache, FP rounding
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README.md
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README.md
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@ -4,18 +4,21 @@ RandomX ("random ex") is an experimental proof of work (PoW) algorithm that uses
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RandomX uses a simple low-level language (instruction set) to describe a variety of random programs. The instruction set was designed specifically for this proof of work algorithm, because existing languages and instruction sets are designed for a different goal (actual software development) and thus usually have a complex syntax and unnecessary flexibility.
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## Virtual machine
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RandomX is intended to be run efficiently and easily on a general-purpose CPU. The virtual machine (VM) which runs RandomX code attempts to simulate a CPU using the following set of components:
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RandomX is intended to be run efficiently and easily on a general-purpose CPU. The virtual machine (VM) which runs RandomX code attempts to simulate a generic CPU using the following set of components:
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#### DRAM
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The VM has access to 4 GiB of external memory in read-only mode. The DRAM memory blob is static within a single PoW epoch. The exact algorithm to generate the DRAM blob and its update schedule is to be determined.
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#### MMU
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The memory management unit (MMU) interfaces the CPU with the DRAM blob. The purpose of the MMU is to translate the random memory accesses generated by the random program into a CPU-friendly access pattern, where memory reads are not bound by DRAM access latency. The MMU splits the 4 GiB DRAM blob into 64-byte blocks (corresponding to the L1 cache line size of a typical CPU). Data within one block is always read sequentially in eight reads (8x8 bytes). Blocks are read mostly sequentially apart from occasional random jumps that happen on average every 1024 blocks. The address of the next block to be read is determined 1 block ahead of time to enable efficient prefetching. The MMU uses three internal registers:
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The memory management unit (MMU) interfaces the CPU with the DRAM blob. The purpose of the MMU is to translate the random memory accesses generated by the random program into a DRAM-friendly access pattern, where memory reads are not bound by access latency. The MMU splits the 4 GiB DRAM blob into 64-byte blocks (corresponding to the L1 cache line size of a typical CPU). Data within one block is always read sequentially in eight reads (8x8 bytes). Blocks are read mostly sequentially apart from occasional random jumps that happen on average every 256 blocks. The address of the next block to be read is determined 1 block ahead of time to enable efficient prefetching. The MMU uses three internal registers:
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* **m0** - Address of the next quadword to be read from memory (32-bit, 8-byte aligned).
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* **m1** - Address of the next block to be read from memory (32-bit, 64-byte aligned).
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* **mx** - Random 64-bit counter that determines if reading continues sequentially or jumps to a random block. When an address `addr` is passed to the MMU, it performs `mx ^= addr` and checks if the last 10 bits of `mx` are zero. If yes, the adjacent 32 bits are copied to register `m1` and 64-byte aligned.
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* **mx** - Random 64-bit counter that determines if reading continues sequentially or jumps to a random block. When an address `addr` is passed to the MMU, it performs `mx ^= addr` and checks if the last 8 bits of `mx` are zero. If yes, the adjacent 32 bits are copied to register `m1` and 64-byte aligned.
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#### Cache
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The VM contains 256 KiB of cache. The cache is split into two segments of 16 KiB and 240 KiB. The cache is randomly accessed for both reading and writing. 75% of accesses are into the first 16 KiB.
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#### Program
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The actual program is stored in a 8 KiB ring buffer structure. Each program consists of 1024 random 64-bit instructions. The ring buffer structure makes sure that the program forms a closed infinite loop.
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@ -30,7 +33,7 @@ The control unit (CU) controls the execution of the program. It reads instructio
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To simulate function calls, the VM uses a stack structure. The program interacts with the stack using the CALL, CALLR and RET instructions. The stack has unlimited size and each stack element is 64 bits wide.
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#### Register file
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The VM has 32 integer registers r0-r31 and 32 floating point registers f0-f31. All registers are 64 bits wide.
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The VM has 8 integer registers r0-r7 and 8 floating point registers f0-f7. All registers are 64 bits wide.
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#### ALU
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The arithmetic logic unit (ALU) performs integer operations. The ALU can perform binary integer operations from 11 groups (ADD, SUB, MUL, DIV, AND, OR, XOR, SHL, SHR, ROL, ROR) with various operand sizes.
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@ -39,126 +42,148 @@ The arithmetic logic unit (ALU) performs integer operations. The ALU can perform
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The floating-point unit performs IEEE-754 compliant math using 64-bit double precision floating point numbers. There are 4 binary operations (ADD, SUB, MUL, DIV) and one unary operation (SQRT).
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## Instruction set
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The 64-bit instruction is structured as follows:
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The 64-bit instruction is encoded as follows:
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##### Opcode
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There are 256 opcodes, which are distributed between various operations depending on their weight (how often it will occur in the program on average). The distribution of opcodes is following:
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#### Opcode (8 bits)
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There are 256 opcodes, which are distributed between various operations depending on their weight (how often they will occur in the program on average). The distribution of opcodes is following:
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|operation|number of opcodes||
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|---------|-----------------|----|
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|ALU operations|TBD|TBD|
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|FPU operations|TBD|TBD|
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|branching|33|13%|
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|branching|32|12.5%|
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##### p1
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p1 (truncated to 5 bits) determines the number of the register, which contains the address of the first operand in DRAM. It is always an integer register even for floating point operations. The content of the register is passed to the MMU as the "address" for reading from DRAM.
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##### p2
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p2 (truncated to 5 bits) determines the number of the second operand register. It is an integer register for ALU operations and a floating point register for FPU operations.
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##### imm0
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An 8-bit immediate value that can be used as an input parameter instead of register p2.
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##### p3
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p3 (truncated to 5 bits) determines the number of the output register. It is an integer register for ALU operations and an floating point register for FPU operations. The result of the operation never overwrites the current value of the output register, but the two values are combined using XOR for integer registers and addition for floating point registers. This is done to make sure the value of a register depends on all previous operations output to this register.
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##### imm1
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An 8-bit immediate value that can be used by the CALL instruction instead of register p3.
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##### imm2
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A 32-bit immediate value that is used by some ALU operations as input instead of register p2.
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#### Parameters a, b, c (8 bits)
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`a` and `b` encode the instruction operands and `c` is the destination. All have the same encoding:
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In the following description of instructions, r(x) refers to an integer register number x, f(x) refers to a floating point register number x and {x} represents the value obtained from the MMU when the value of integer register r(x) is passed as the read address.
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Register number is encoded in the top 3 bits. ALU instructions use registers r0-r7, while FPU instructions use registers f0-f7. Addresses are always loaded from registers r0-r7. The bottom 3 bits determine where the operand is loaded from/result saved to:
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|location|a|b|c|
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|---------|-|-|-
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|000|register|register|register|
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|001|register|register|register|
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|010|register|register|register|
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|011|cache|register|cache|
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|100|cache|register|cache|
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|101|DRAM|register|cache|
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|110|DRAM|imm1|cache|
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|111|DRAM|imm1|cache|
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* **register** - Direct register read/write.
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* **cache** - The value of the register is used as an address to read from/write to the cache. The bottom 3 bits of the address are cleared and the address is truncated to the following length depending on the cache bits:
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|cache|address length|
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|---------|-|
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|00|18 bits (whole 256 KiB)|
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|01|14 bits (first 16 KiB)|
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|10|14 bits (first 16 KiB)|
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|11|14 bits (first 16 KiB)|
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* **DRAM** - The value of the register is used as an address to pass to the MMU.
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* **imm1** - 32-bit immediate value encoded within the instruction. For ALU instructions that use operands shorter than 32 bits, the value is truncated. For operands larger than 32 bits, the value is zero-extended for unsigned instructions and sign-extended fot signed instructions. For FPU instructions, the value is treated as a signed 32-bit integer, first converted to a single precision floating point format and then to a double precision format.
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#### imm0 (8 bits)
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An 8-bit immediate value that is used by the CALL instruction as jump offset.
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### ALU instructions
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All ALU instructions take 2 operands A and B and produce result C. If the operand size is smaller than the input size, the input is truncated. If the operand size is larger than the input size, the input is sign-extended for signed operations and zero-extended for unsigned (this applies to operations using *imm2*).
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All ALU instructions take 2 operands A and B and produce result C.
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After C is calculated, every ALU instruction performs `r(p3) ^= C`.
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|opcodes|instruction|signed|A|A width|B|B width|C|C width|
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|opcodes|instruction|signed|A width|B width|C|C width|
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|-|-|-|-|-|-|-|-|-|
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|TBD|ADD_U64|no|{p1}|64|r(p2)|64|A + B|64|
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|TBD|ADD_U32|no|{p1}|32|r(p2)|32|A + B|32|
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|TBD|ADD_U16|no|{p1}|16|r(p2)|16|A + B|16|
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|TBD|ADD_UC64|no|{p1}|64|imm2|64|A + B|64|
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|TBD|ADD_UC32|no|{p1}|32|imm2|32|A + B|32|
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|TBD|SUB_U64|no|{p1}|64|r(p2)|64|A - B|64|
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|TBD|SUB_U32|no|{p1}|32|r(p2)|32|A - B|32|
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|TBD|SUB_U16|no|{p1}|16|r(p2)|16|A - B|16|
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|TBD|SUB_UC64|no|{p1}|64|imm2|64|A - B|64|
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|TBD|SUB_UC32|no|{p1}|32|imm2|32|A - B|32|
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|TBD|MUL_U64|no|{p1}|64|r(p2)|64|A * B|64|
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|TBD|MUL_U32|no|{p1}|32|r(p2)|32|A * B|64|
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|TBD|MUL_I32|yes|{p1}|32|r(p2)|32|A * B|64|
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|TBD|MUL_U16|no|{p1}|16|r(p2)|16|A * B|32|
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|TBD|MUL_I16|yes|{p1}|16|r(p2)|16|A * B|32|
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|TBD|MUL_UC64|no|{p1}|64|imm2|64|A * B|64|
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|TBD|MUL_UC32|no|{p1}|32|imm2|32|A * B|64|
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|TBD|MUL_IC32|yes|{p1}|32|imm2|32|A * B|64|
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|TBD|DIV_U64|no|{p1}|64|r(p2)|32|A / B, A % B|64|
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|TBD|DIV_I64|yes|{p1}|64|r(p2)|32|A / B, A % B|64|
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|TBD|DIV_U32|no|{p1}|32|r(p2)|16|A / B, A % B|32|
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|TBD|DIV_I32|yes|{p1}|32|r(p2)|16|A / B, A % B|32|
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|TBD|AND_U64|no|{p1}|64|r(p2)|64|A & B|64|
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|TBD|AND_U32|no|{p1}|32|r(p2)|32|A & B|32|
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|TBD|AND_U16|no|{p1}|16|r(p2)|16|A & B|16|
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|TBD|AND_UC64|no|{p1}|64|imm2|64|A & B|64|
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|TBD|AND_UC32|no|{p1}|32|imm2|32|A & B|32|
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|TBD|OR_U64|no|{p1}|64|r(p2)|64|A | B|64|
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|TBD|OR_U32|no|{p1}|32|r(p2)|32|A | B|32|
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|TBD|OR_U16|no|{p1}|16|r(p2)|16|A | B|16|
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|TBD|OR_UC64|no|{p1}|64|imm2|64|A | B|64|
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|TBD|OR_UC32|no|{p1}|32|imm2|32|A | B|32|
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|TBD|XOR_U64|no|{p1}|64|r(p2)|64|A ^ B|64|
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|TBD|XOR_U32|no|{p1}|32|r(p2)|32|A ^ B|32|
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|TBD|XOR_U16|no|{p1}|16|r(p2)|16|A ^ B|16|
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|TBD|XOR_UC64|no|{p1}|64|imm2|64|A ^ B|64|
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|TBD|XOR_UC32|no|{p1}|32|imm2|32|A ^ B|32|
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|TBD|SHL_U64|no|{p1}|64|r(p2)|6|A << B|64|
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|TBD|SHL_UC64|no|{p1}|64|imm0|6|A << B|64|
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|TBD|SHR_U64|no|{p1}|64|r(p2)|6|A >> B|64|
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|TBD|SHR_UC64|no|{p1}|64|imm0|6|A >> B|64|
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|TBD|SHR_I64|yes|{p1}|64|r(p2)|6|A >> B|64|
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|TBD|SHR_IC64|yes|{p1}|64|imm0|6|A >> B|64|
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|TBD|ROL_U64|no|{p1}|64|r(p2)|6|A <<< B|64|
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|TBD|ROL_UC64|no|{p1}|64|imm0|6|A <<< B|64|
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|TBD|ROR_U64|no|{p1}|64|r(p2)|6|A >>> B|64|
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|TBD|ROR_UC64|no|{p1}|64|imm0|6|A >>> B|64|
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|TBD|ADD_64|no|64|64|A + B|64|
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|TBD|ADD_32|no|32|32|A + B|32|
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|TBD|ADD_16|no|16|16|A + B|16|
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|TBD|SUB_64|no|64|64|A - B|64|
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|TBD|SUB_32|no|32|32|A - B|32|
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|TBD|SUB_16|no|16|16|A - B|16|
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|TBD|MUL_64|no|64|64|A * B|64|
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|TBD|MUL_32|no|32|32|A * B|64|
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|TBD|MUL_16|no|16|16|A * B|32|
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|TBD|IMUL_32|yes|32|32|A * B|64|
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|TBD|IMUL_16|yes|16|16|A * B|32|
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|TBD|DIV_64|no|64|32|A / B, A % B|64|
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|TBD|IDIV_64|yes|64|32|A / B, A % B|64|
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|TBD|DIV_32|no|32|16|A / B, A % B|32|
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|TBD|IDIV_32|yes|32|16|A / B, A % B|32|
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|TBD|AND_64|no|64|64|A & B|64|
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|TBD|AND_32|no|32|32|A & B|32|
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|TBD|AND_16|no|16|16|A & B|16|
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|TBD|OR_64|no|64|64|A | B|64|
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|TBD|OR_32|no|32|32|A | B|32|
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|TBD|OR_16|no|16|16|A | B|16|
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|TBD|XOR_64|no|64|64|A ^ B|64|
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|TBD|XOR_32|no|32|32|A ^ B|32|
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|TBD|XOR_16|no|16|16|A ^ B|16|
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|TBD|SHL_64|no|64|6|A << B|64|
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|TBD|SHR_64|no|64|6|A >> B|64|
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|TBD|SAR_64|yes|64|6|A >> B|64|
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|TBD|ROL_64|no|64|6|A <<< B|64|
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|TBD|ROR_64|no|64|6|A >>> B|64|
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##### Division
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For the division instructions, the divisor is half length of the dividend. The result `C` consists of both the quotient and the remainder (remainder is put the upper bits). The result of division by zero is equal to the dividend.
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##### Result write-back
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If `C` is shorter than 64 bits, it is zero-extended before the result is written back. If the destination is a register, the value is first encrypted with a single AES round (TBD).
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### FPU instructions
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Floating point instructions take two operands A and B and produce result C (except the SQRT_F64 instruction, which only takes one operand). After C is calculated, every FPU instruction performs `f(p3) += C`. The order of operations must be preserved since floating point math is not associative.
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|opcodes|instruction|A|B|C|
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|opcodes|instruction|C|
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|-|-|-|-|-|
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|TBD|ADD_F64|double({p1})|f(p2)|A + B|
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|TBD|SUB_F64|double({p1})|f(p2)|A - B|
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|TBD|MUL_F64|double({p1})|f(p2)|A * B|
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|TBD|DIV_F64|double({p1})|f(p2)|A / B|
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|TBD|SQRT_F64|abs(double({p1}))|-|sqrt(A)|
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|TBD|FADD|A + B|
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|TBD|FSUB|A - B|
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|TBD|FMUL|A * B|
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|TBD|FDIV|A / B|
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|TBD|FSQRT|sqrt(A)|
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|TBD|FROUND|-|
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FPU instructions conform to the IEEE-754 specification. Initial rounding mode is RN (Round to Nearest). Denormal values are treated as zero (this corresponds to setting the FTZ flag in x86 SSE and ARM Neon engines).
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Operands loaded from memory are treated as signed 64-bit integers and converted to double precision floating point format. Operands loaded from floating point registers are used directly.
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##### FSQRT
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The sign bit of the FSQRT operand is always cleared first, so only non-negative values are evaluated.
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##### FROUND
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The FROUND instruction changes the rounding mode for all subsequent FPU operations depending on the two right-most bits of A:
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|A[1:0]|rounding mode|
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|-------|------------|
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|00|Round to Nearest (RN) mode|
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|01|Round towards Plus Infinity (RP) mode
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|10|Round towards Minus Infinity (RM) mode
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|11|Round towards Zero (RZ) mode
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### Branch instructions
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The CU supports 3 branch instructions:
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|opcodes|instruction|function|
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|-|-|-|
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|223-242|CALL|conditional near procedure call with static offset|
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|243-246|CALLR|conditional near procedure call with register offset|
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|247-255|RET|conditional return from procedure|
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|TBD|CALL|conditional near procedure call with static offset|
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|TBD|CALLR|conditional near procedure call with register offset|
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|TBD|RET|conditional return from procedure|
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All three instructions are conditional: the jump happens only if `(r(p2) & 0xFFFFFFFF) < imm2`. In case the branch is not taken, all three instructions perform `r(p3) ^= {p1}` ("arithmetic no-op").
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All three instructions are conditional. Branching pattern is determined by the value of `imm1` (exact mechanism TBD). In case the branch is not taken, all three instructions set `C = A` ("arithmetic no-op").
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##### CALL and CALLR
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When the branch is taken, both CALL and CALLR instructions push the values `{p1}` (value read from DRAM) and `pc` (program counter) onto the stack and then perform a forward jump relative to the value of `pc`. The forward offset is equal to `8 * (imm1 + 1)` for the CALL instruction and `8 * ((r(p3) & 0xFF) + 1)` for the CALLR instruction. Maximum jump distance is therefore 256 instructions forward (this means that at least 4 correctly spaced CALL/CALLR instructions are needed to form a loop in the program).
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When the branch is taken, both CALL and CALLR instructions push the values `A` and `pc` (program counter) onto the stack and then perform a forward jump relative to the value of `pc`. The forward offset is equal to `8 * (imm0 + 1)` for the CALL instruction and `8 * ((C & 0xFF) + 1)` for the CALLR instruction. Maximum jump distance is therefore 256 instructions forward (this means that at least 4 correctly spaced CALL/CALLR instructions are needed to form a loop in the program).
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##### RET
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When the branch is taken, the RET instruction pops the return address `raddr` from the stack (it's the instructions following the corresponding CALL or CALLR), then pops a return value `retval` from the stack and performs `r(p3) ^= retval`. Finally, the instruction jumps back to `raddr`.
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When the branch is taken, the RET instruction pops the return address `raddr` from the stack (it's the instructions following the corresponding CALL or CALLR), then pops a return value `retval` from the stack and sets `C = retval`. Finally, the instruction jumps back to `raddr`.
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## Program generation
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The program is initialized from a 256-bit seed value using a suitable PRNG. The program is generated in this order:
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1. All 1024 instructions are generated as a list of random 64-bit integers.
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2. Initial values of all integer registers r0-r31 are generated as random 64-bit integers.
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3. Initial values of all floating point registers f0-f31 are generated as random 64-bit integers converted to a double precision floating point format.
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2. Initial values of all integer registers r0-r7 are generated as random 64-bit integers.
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3. Initial values of all floating point registers f0-f7 are generated as random 64-bit signed integers converted to a double precision floating point format.
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4. The initial value of the `m0` register is generated as a random 32-bit value with the last 6 bits cleared (64-byte aligned).
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5. The remaining registers are initialized as `pc = 0`, `sp = 0`, `ic = 65536`, `m1 = m0 + 64`, `mx = 0`.
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5. The 256 KiB cache is initialized using AES encryption (TBD).
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6. The remaining registers are initialized as `pc = 0`, `sp = 0`, `ic = 65536`, `m1 = m0 + 64`, `mx = 0`.
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## Result
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When the program terminates (the value of `ic` register reaches 0), the register file and the stack are hashed using the Blake2b has function to get the final PoW value. The generation/execution can be chained multiple times to discourage mining strategies that search for programs with particular properties.
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When the program terminates (the value of `ic` register reaches 0), the register file and the stack are hashed using the Blake2b hash function to get the final PoW value. The generation/execution can be chained multiple times to discourage mining strategies that search for programs with particular properties.
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Reference in New Issue